UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 177
UPD78F0552MA-FAA-AX
Manufacturer Part Number
UPD78F0552MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0552MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2-L
(1) 78K0/KB2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or
P12:
PU12:
PM12:
RD:
WR××: Write signal
WR
WR
WR
RD
PORT
PM
PU
2. RESET/P125 is set in an external reset input after a reset release.
3. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
4. If using P120 to input the potential for an external low-voltage detector, connect P120 to the
subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or
subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock
input mode must be set by using the clock operation mode select register (OSCCTL) (for details,
refer to 5.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode
for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are
Input port pins).
signal is generated during low level input, the reset status continues until the input rises to the
high level.
measured voltage source through a resistor. Do not apply a voltage of V
Port register 12
Pull-up resistor option register 12
Port mode register 12
Read signal
Output latch
Alternate
function
PM120
PU120
(P120)
PM12
PU12
P12
Figure 4-27. Block Diagram of P120 (1/2)
CHAPTER 4 PORT FUNCTIONS
V
DD
DD
P-ch
or more to P120.
P120/INTP0/EXLVI
163
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