UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 115

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
FF20H
FF21H
FF22H
FF23H
FF24H
FF25H
FF26H
FF27H
FF28H
FF29H
FF2AH
FF2BH
FF2CH
FF2DH
FF2EH
FF2FH
FF30H
FF31H
FF32H
FF33H
FF34H
FF35H
FF36H
FF37H
FF38H to
FF3BH
FF3CH
FF3DH
FF3EH
FF3FH
Address
78K0/Kx2-L
Notes 1. 48-pin products only.
Remark
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
2. 44-pin and 48-pin products only.
PM0
PM1
PM2
PM3
PM4
PER0
PM6
PM7
ADM0
POM6
FPCTL
PM12
RSTMASK
ADPC0
ADPC1
PU0
PU1
PU3
PU4
PU6
PU7
PU12
RMC
PIM6
MUXSEL
Symbol
For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
Note2
Note2
−
−
−
−
Note2
<ADCS>
ADPCS7 ADPCS6 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
PM27
RTCEN
PM17
PU17
7
1
−
−
−
−
−
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Note2
PM16
PM26
PU16
−
−
−
−
−
6
1
1
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Table 3-10. Special Function Register List: 78K0/KC2-L (2/6)
PU125
RSTM
PM15
PM25
PM75
PU15
PU75
FR2
Note 1
Note 1
5
1
1
1
0
1
−
0
0
1
0
0
−
0
0
−
0
−
−
0
0
PM14
PM24
PM74
PU14
PU74
FR1
Note 1
Note 1
4
1
1
1
0
1
−
0
0
1
0
0
0
−
0
0
−
0
−
0
−
0
0
Bit No.
POM63
PM13
PM23
PM33
PM63
PM73
PU13
PU33
PU63
PU73
FR0
Note2
Note2
Note2
−
−
−
−
−
3
1
1
0
0
1
0
0
0
0
0
0
0
CSISEL
POM62 POM61 POM60
ADPCS10 ADPCS9 ADPCS8
PM02
PM12
PM22
PM32
PM42
PM62
PM72
PU02
PU12
PU32
PU42
PU62
PU72
Note 1
Note 1
LV1
Note 1
Note 1
−
−
−
−
−
2
0
0
1
0
0
0
PIM61
PM01
PM11
PM21
PM31
PM41
PM61
PM71
PU01
PU11
PU41
PU61
PU71
PU31
LV0
Note2
Note2
1
0
−
0
1
0
−
−
−
0
−
0
<ADCE>
<FLMD
PM120
PU120
PIM60
PM00
PM10
PM20
PM30
PM40
PM60
PM70
PUP>
PU00
PU10
PU30
PU40
PU60
PU70
Note2
Note2
0
0
−
0
−
−
−
−
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
−
−
CHAPTER 3 CPU ARCHITECTURE
1
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
−
√
√
−
√
√
−
√
−
√
√
Simultaneously
Number of Bits
Manipulated
−
−
−
−
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Reset
After
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
07H
00H
00H
00H
00H
00H
00H
20H
00H
00H
00H
−
−
−
−
167, 324,
345, 415,
440, 463,
167, 415,
167, 324,
167, 385,
167, 573,
181, 413,
167, 463,
167, 256
400, 573
183, 572
504, 573
180, 464,
179, 503
212, 373
573
440
345
167
405
713
676
180
437
177
177
177
177
177
177
177
691
504
−
−
−
−
101