SAK-TC1766-192F80HL BD Infineon Technologies, SAK-TC1766-192F80HL BD Datasheet - Page 35

• Manufacturer Part Number: SAK-TC1766-192F80HL BD
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1766-192F80HL BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 108K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 108.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.5 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1766192F80HLBDXT; SAK-TC1766-192F80HLBDINTR

Preliminary
3.6
The DMA Controller of the TC1766 transfers data from data source locations to data
destination locations without intervention of the CPU or other on-chip devices. One data
move operation is controlled by one DMA channel. Eight DMA channels are provided in
one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to
the two FPI Bus interfaces and an MLI bus interface. In the TC1766, the FPI Bus
interfaces are connected to the System Peripheral Bus and the DMA Bus. The third
specific bus interface provides a connection to Micro Link Interface modules (two MLI
modules in the TC1766) and other DMA-related devices (Memory Checker module in the
TC1766). Clock control, address decoding, DMA request wiring, and DMA interrupt
service request control are implementation-specific and managed outside the DMA
controller kernel.
the DMA module.
Figure 3-2
Data Sheet
Requests
Decoder
Interrupt
Request
On-chip
Address
Control
Periph.
Nodes
Clock
Units
DMA
of
DMA Controller and Memory Checker
SR[15:0]
DMA Controller Block Diagram
f
DMA
Figure 3-2
CH0n_OUT
Selection/
Arbitration
Request
DMA Interrupt Control
shows the implementation details and interconnections of
DMA Sub-Block 0
DMA Controller
Transaction
Control Unit
Channels
00-07
DMA
31
Arbiter/
Control
Switch
Switch
Bus
Functional Description
V1.0, 2008-04
System
Periphera
Bus
DMA Bus
Checker
Memory
MCB06149
MLI0
MLI1
TC1766