SAK-TC1766-192F80HL BD Infineon Technologies, SAK-TC1766-192F80HL BD Datasheet - Page 37

• Manufacturer Part Number: SAK-TC1766-192F80HL BD
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1766-192F80HL BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 108K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 108.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.5 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1766192F80HLBDXT; SAK-TC1766-192F80HLBDINTR

Preliminary
Note: Although the polynomial above is used for generation, the generation algorithm
3.7
The TC1766 interrupt system provides a flexible and time-efficient means of processing
interrupts. An interrupt request can be serviced either by the CPU or by the Peripheral
Control Processor (PCP). These units are called “Service Providers”. Interrupt requests
are called “Service Requests” rather than “Interrupt Requests” in this document because
they can be serviced by either Service Providers.
Each peripheral in the TC1766 can generate service requests. Additionally, the Bus
Control Units, the Debug Unit, the PCP, and even the CPU itself can generate service
requests to either of the two Service Providers.
As shown in
connected to one or multiple Service Request Nodes (SRN). Each SRN contains a
Service Request Control Register mod_SRCx, where “mod” is the identifier of the
service requesting unit and “x” an optional index. Two arbitration buses connect the
SRNs with two Interrupt Control Units, which handle interrupt arbitration among
competing interrupt service requests, as follows:
•
•
The PCP can make service requests directly to itself (via the PICU), or it can make
service requests to the CPU. The Debug Unit can generate service requests to the PCP
or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can
make service requests to the PCP. The CPU Service Request Nodes are activated
through software.
Depending on the selected system clock frequency f
per arbitration cycle must be selected as follows:
•
•
Data Sheet
The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and
administers the CPU Interrupt Arbitration Bus.
The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP
and administers the PCP Interrupt Arbitration Bus.
f
f
SYS
SYS
differs from the one that is used by the Ethernet protocol.
< 60 MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1
> 60 MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0
Interrupt System
Figure
3-3, each TC1766 unit that can generate service requests is
33
SYS
, the number of f
Functional Description
SYS
V1.0, 2008-04
clock cycles
TC1766