IP-CPRI Altera, IP-CPRI Datasheet - Page 103

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Software Interface
CPRI Interface Registers
Table 6–13. CPRI_PHY_LOOP—Physical Layer Loopback Control—Offset: 0x24 (Part 2 of 2)
Table 6–14. CPRI_CM_CONFIG—CPRI Control and Management Configuration—Offset: 0x28
Table 6–15. CPRI_CM_STATUS—CPRI Control and Management Status—Offset: 0x2C (Part 1 of 2)
December 2010 Altera Corporation
loop_mode
Note to
(1) This register field is a read-to-clear field. You must read the register twice to read the true value of the field after frame synchronization is
RSRV
tx_slow_cm_rate
RSRV
tx_fast_cm_ptr
RSRV
rx_slow_cm_rate_valid
achieved. If you observe this bit asserted during link initialization, read the register again after link initialization to confirm any errors.
Table
Field
Field
6–13:
Field
[0]
[31:11] UR0
[10:8]
[7:6]
[5:0]
Bits
Bits
[31:12] UR0
[11]
Bits
RW
RW
UR0
RW
Access
Access
RO
Access
Physical layer loopback mode. The following values are
defined:
This loopback mode takes precedence over the 3-bit
loop_mode specified in the CPRI_CONFIG register at offset
0x8: if this field has value 1, the 3-bit loop_mode value is
ignored.
Reserved.
Rate configuration for slow C&M (HDLC). To be inserted in
CPRI control byte Z.66.0.
Reserved.
Pointer to first CPRI control word used for fast C&M
(Ethernet). To be inserted in CPRI control byte Z.194.0.
0: No loopback.
1: Full CPRI frame loop. Incoming CPRI data and control
words are sent back as-is in outgoing CPRI
communication. This low-level reverse loopback path is
active whether or not frame synchronization has been
achieved; the path includes 8B/10B encoding and
decoding, but only enough core CPRI functionality to
handle the transition from the receiver clock domain to the
transmitter clock domain.
Reserved.
Indicates that a valid slow C&M rate has been accepted.
Function
Function
Function
CPRI MegaCore Function User Guide
2'h0
20'h0
3’h0
2'h0
8'h24
Default
Default
20’h0
1'h0
Default
6–7