IP-CPRI Altera, IP-CPRI Datasheet - Page 117

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Software Interface
Ethernet Registers
Table 6–52. ETH_CONFIG_2—Ethernet Feature Configuration 2—Offset: 0x20C
Table 6–53. ETH_RX_CONTROL—Ethernet Rx Control—Offset: 0x210
Table 6–54. ETH_RX_DATA—Ethernet Rx Data—Offset: 0x214
Table 6–55. ETH_RX_DATA_WAIT—Ethernet Rx Data with Wait-State Insertion—Offset: 0x218
Table 6–56. ETH_TX_CONTROL—Ethernet Tx Control—Offset: 0x21C
December 2010 Altera Corporation
RSRV
crc_enable
RSRV
rx_discard
rx_data
rx_data
RSRV
tx_length
tx_discard
tx_eop
Field
Field
Field
Field
Field
[31:1] UR0
[0]
[31:1] RO
[0]
[31:0] RO
[31:0] RO
[31:4] UR0
[3:2]
[1]
[0]
Bits
Bits
Bits
Bits
Bits
RW
WO
WO
WO
WO
Access
Access
Access
Access
Access
Reserved.
Enables insertion of Ethernet frame check sequence (FCS) at the end
of the Ethernet frame.
Reserved.
Indicates that the Ethernet receiver module should discard the
current Ethernet Rx frame.
Ethernet Rx frame data. If the Ethernet receiver module takes
Ethernet data from this register, if data is not ready when the module
expects it, the Ethernet receiver module aborts the packet.
Ethernet Rx frame data. If the Ethernet receiver module takes
Ethernet data from this register, it inserts wait states on the Ethernet
channel until data is ready, unless the CPU times out the operation.
Reserved.
Length of the final word in the packet. Values are:
This field is valid when the tx_eop bit is asserted.
Indicates that the Ethernet transmitter module should discard the
current Ethernet Tx frame.
Indicates that the next data word to be written to the ETH_TX_DATA
or ETH_TX_DATA_WAIT register contains the end-of-packet byte for
this Tx packet.
00: 1 valid byte
01: 2 valid bytes
10: 3 valid bytes
11: 4 valid bytes
Function
Function
Function
Function
Function
CPRI MegaCore Function User Guide
31'h0
1'h0
31'h0
1'h0
1'h0
1'h0
28'h0
1’h0
1'h0
1’h0
Default
Default
Default
Default
Default
6–21