IP-CPRI Altera, IP-CPRI Datasheet - Page 131

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Testbenches
Running the Testbenches
December 2010 Altera Corporation
3. If you are running the tb_altera_cpri_autorate or tb_altera_cpri_c4gx_autorate
4. If you are using ModelSim SE or ModelSim AE, turn off simulation optimization
testbench, you must generate the appropriate Memory Initialization Files (.mif) to
configure the altgx_reconfig block. If you are running the
tb_altera_cpri_c4gx_autorate testbench, the following steps also generate the
appropriate Memory Initialization Files (.mif) to configure the altpll_reconfig
block. To generate the files, follow these steps:
a. On the Assignments menu, click Settings.
b. In the Settings dialog box, under Category, click Fitter Settings.
c. Click More Settings.
d. Turn on Generate GXB Reconfig MIF.
e. Click OK.
f. Click Apply.
g. Click OK.
h. On the Processing menu, click Start Compilation.
i. In the MegaWizard Plug-in Manager, edit the existing CPRI DUT, change its
j. Repeat step h. A new set of .mif files is generated for the new data rate.
k. Move all of the .mif files from the reconfig_mif subdirectory to your testbench
l. Edit the rom_stratix4gx_<rate>_m.vhd or
m. In the MegaWizard Plug-in Manager, edit the existing CPRI DUT to return it to
by performing the following steps:
a. In the ModelSim simulator, on the Compile menu, click Compile Options.
b. Perform one of the following actions:
c. Click Apply.
d. Click OK.
After compilation completes, the following newly generated .mif files are
available, depending on your target device:
reconfig_mif/cyclone4gx_<rate>_m.mif, cyclone4gx_<rate>_m_rx_pll1.mif,
cyclone4gx_<rate>_m_tx_pll0.mif, reconfig_mif/stratix4gx_<rate>_m.mif.
data rate to 1.228 Gbps, and regenerate.
directory, <working directory>/cpri_top_level_testbench/altera_cpri.
rom_cyclone4gx_<rate>_reconfig.vhd files to remove the string
alt<chars>gxb from the .mif file names.
its original data rate of 0.6144 Gbps, and regenerate.
i. If you are using the ModelSim SE simulator, in the Compiler Options dialog
ii. If you are using the ModelSim AE simulator, on the VHDL tab and on the
box, on the VHDL tab, turn off Use vopt flow.
Verilog & System Verilog tab, turn on Disable optimizations by using
-O0.
CPRI MegaCore Function User Guide
7–7