IP-CPRI Altera, IP-CPRI Datasheet - Page 78

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–54
Figure 4–23. CPRI MII Interface Transmitter Example 1
Figure 4–24. CPRI MII Interface Transmitter Example 2
CPRI MegaCore Function User Guide
cpri_mii_txd[3:0]
decoded result
cpri_mii_txd[3:0]
cpri_mii_txclk
cpri_mii_txen
decoded result
cpri_mii_txrd
cpri_mii_txer
(conceptual)
cpri_mii_txclk
cpri_mii_txen
cpri_mii_txrd
cpri_mii_txer
(conceptual)
Figure 4–23
no input errors.
Although
cycle in which cpri_mii_txrd is not asserted, your external Ethernet block may
optionally keep the cpri_mii_txen signal asserted continuously for the duration of
the packet.
duration of the packet transfer. In addition, although
cpri_mii_txrd reasserted every other cycle during transmission of an Ethernet packet
on cpri_mii_txd, this need not always occur. The CPRI MII Interface transmitter can
deassert cpri_mii_txrd for more than one cycle to backpressure the external Ethernet
block. In that case, the external Ethernet block must maintain the data value on
cpri_mii_txd until the cycle following reassertion of cpri_mii_txrd.
txen response
txrd asserted
Figure 4–23
txen response
txrd asserted
Figure 4–24
>1 cycle
without
and
Idle
>1 cycle
without
Idle
Figure 4–24
2 cycles in which
txrd is asserted
txen asserted
J
txen asserted
J
shows cpri_mii_txen continually deasserted following each
2 cycles
shows a case in which cpri_mii_txen remains asserted for the
K
K
both illustrate the MII interface transmitter protocol with
D0
D0
to backpressure the Ethernet block
D0
D0
D1
D1
D1
D1
an additional cycle
txrd is deasserted
D2
D2
Ethernet packet
Ethernet packet
D2
D2
D3
D3
D3
D3
Figure 4–23
D4
D4
D4
D4
MII Interface to an External Ethernet Block
D5
D5
December 2010 Altera Corporation
Chapter 4: Functional Description
D5
D5
No txen response
txrd asserted
No txen response
T
to 2 cycles
shows
txrd asserted
in which
T
to 2 cycles
in which
R
R
Idle
Idle