IP-CPRI Altera, IP-CPRI Datasheet - Page 39

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Clocking and Reset Structure
December 2010 Altera Corporation
Reset Control Word Communicated on CPRI Link
In addition, a CPRI MegaCore function can receive or send a reset request through the
CPRI link. You use the CPRI MegaCore function CPRI_HW_RESET register, and
optionally the hw_reset_assert input signal, to control and monitor the reset control
word sent in CPRI communication. As dictated by the CPRI specification, the reset
control information is sent in bit 0 of the CPRI hyperframe control word Z.130.0. This
reset bit is used for both reset request and reset acknowledge.
A CPRI MegaCore function in master mode transmits a reset request to the RE slave
nodes to which it is connected under either of the following conditions:
■
■
The behavior of a CPRI MegaCore function in slave mode that receives a reset request
on the CPRI link depends on the same enable fields in its own CPRI_HW_RESET register.
For reset acknowledgements, the reset_hw_en bit also takes precedence over the
reset_gen_en bit. If the reset_hw_en bit is asserted, the reset_gen_en bit is ignored.
The following sections describe the CPRI MegaCore function behavior in sending and
receiving reset requests and reset acknowledgements under the two different sets of
conditions.
CPRI Link Reset Requests and Acknowledgements Based on reset_gen_force Register Field
The CPRI specification dictates that the Z.130.0 reset bit must be detected by the CPRI
partner in four consecutive hyperframes before the CPRI partner confirms the reset
request. The reset generation request is in effect while reset_gen_force remains set,
until the reset acknowledge control bit is detected on the incoming CPRI link, as long
as the reset_gen_en bit remains high.
To abort a reset request made by asserting the reset_gen_force bit in the
CPRI_HW_RESET register, set the reset_gen_en bit of the CPRI_HW_RESET register to 0.
A CPRI MegaCore function in slave mode indicates that it detects a reset request sent
in CPRI communication by setting the reset_detect and reset_detect_hold bits of
the CPRI_HW_RESET register. If the reset_gen_en bit is set (and the reset_hw_en bit is
not set), the CPRI transmitter sends a reset acknowledge on the CPRI link, by setting
the Z.130.0 reset bit in ten consecutive outgoing hyperframes. If the reset_out_en bit
is set, the CPRI MegaCore function asserts the external hw_reset_req signal until the
reset occurs. This signal informs the application layer of the low-level reset request.
After it transmits the ten consecutive reset acknowledge bits, the CPRI transmitter
sets the reset_gen_done and reset_gen_done_hold bits.
For more information about the CPRI_HW_RESET register, refer to
page
After reset, software must perform link synchronization and other initialization tasks.
For information about the required initialization sequence following CPRI MegaCore
function reset, refer to
The reset_gen_en and reset_gen_force bits in the CPRI_HW_RESET register are set,
and the reset_hw_en bit in the CPRI_HW_RESET register is not set.
The hw_reset_assert input signal is asserted while the reset_hw_en bit in the
CPRI_HW_RESET register is set.
6–5.
Appendix A, Initialization
Sequence.
CPRI MegaCore Function User Guide
Table 6–12 on
4–15