IP-CPRI Altera, IP-CPRI Datasheet - Page 138

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–2
Figure B–1. Auto-Rate Negotiation in Slave Clocking Mode
Notes for
(1) Optional clock switching logic determines the value of gxb_refclk, depending on the desired transceiver frequency setting.
(2) You must reset the cleanup PLL configuration for different incoming and outgoing clock frequencies when the CPRI line rate changes.
(3) The number of ROMs and the rate requirements are design dependent.
CPRI MegaCore Function User Guide
Figure
(3)
frame synchronization
line rate based on
Software controls
FSM feedback.
B–1:
614.4 Mbps
MIF file in
1228.8 Mbps
MIF file in
2457.6 Mbps
MIF file in
6144.0 Mbps
MIF file in
3072.0 Mbps
MIF file in
4915.2 Mbps
MIF file in
ROM
ROM
ROM
ROM
ROM
ROM
Figure B–1
for CPRI MegaCore functions in slave clocking mode and master clocking mode,
respectively. The diagrams show all the potential CPRI line rates for an Arria II GX,
Arria II GZ, or Stratix IV GX device. However, if you remove the options for the two
highest CPRI line rates, the examples are functional for Cyclone IV GX devices. The
examples clarify the functionality provided by the CPRI MegaCore function, and the
logic and data you must configure in your design outside the MegaCore function.
(3)
614.4 Mbps
MIF file in
1228.8 Mbps
MIF file in
3072.0 Mbps
MIF file in
2457.6 Mbps
MIF file in
ROM
ROM
ROM
ROM
and
Line Rate
GPLL
Figure B–2
(1)
122.88 MHz
15.36 MHz
30.72 MHz
61.44 MHz
153.6 MHz
76.8 MHz
show example auto-rate negotiation logic block diagrams
ALTPLL_RECONFIG
ALTGX_RECONFIG
(for Cyclone IV GX
devices)
Cleanup PLL
Appendix B: Implementing CPRI Link Auto-Rate Negotiation
gxb_refclk
(2)
gxb_pll_inclk
AUTORATE_CONFIG
Register
CPRI MegaCore Function
rx_cruclk
pll_clkout
pll_inclk
reconfig_fromgxb
reconfig_togxb
To MPLL
in Cyclone IV GX
devices
December 2010 Altera Corporation
datarate_en
datarate_set
ALTGX
Design Implementation