IP-CPRI Altera, IP-CPRI Datasheet - Page 77

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
MII Interface to an External Ethernet Block
December 2010 Altera Corporation
ready to provide data. The MII interface transmitter module deasserts the
cpri_mii_txrd signal in the cycle following each cycle in which it receives data. It
may remain deasserted for multiple cycles, to prevent buffer overflow. While the
cpri_mii_txrd signal remains low, the external Ethernet block must maintain the data
value on cpri_mii_txd.
During the first cpri_mii_txclk cycle in which cpri_mii_txen is asserted, the MII
interface module inserts an Ethernet J symbol (5’b11000) in the buffer of data to be
transmitted to the CPRI link; during the second cycle in which cpri_mii_txen is
asserted, the MII interface module inserts an Ethernet K symbol (5’b10001) in this
buffer. These two symbols indicate Ethernet start-of-packet. While the CPRI MII
Interface transmitter is inserting the J and K symbols, it ignores incoming data on
cpri_mii_txd. Refer to
Typically, the external Ethernet block asserts cpri_mii_txen one clock cycle after
cpri_mii_txrd is asserted. If not, after the initial cycle in which cpri_mii_txrd is
asserted, while cpri_mii_txrd continues to be asserted but cpri_mii_txen is not yet
asserted, the CPRI MII Interface transmitter inserts an Idle cycle in the buffer of data
to be transmitted to the CPRI link. After cpri_mii_txen is asserted following the
assertion of cpri_mii_txrd, if cpri_mii_txen is subsequently deasserted following a
cycle in which cpri_mii_txrd remains asserted, the CPRI MII Interface transmitter
assumes the external Ethernet block has reached end-of-frame, and begins insertion of
the Ethernet end-of-packet symbol (T followed by R). While the CPRI MII Interface
transmitter is inserting the T and R symbols, it ignores incoming data on
cpri_mii_txd. Refer to
While the cpri_mii_txen signal remains asserted or is continually reasserted in
response to assertion of cpri_mii_txrd, the MII interface transmitter module reads
data on the cpri_mii_txd input data bus. Following this data sequence, in the first
two cpri_mii_txclk cycles in which the cpri_mii_txen signal is not asserted in
response to the MII interface module asserting cpri_mii_txrd, the MII interface
module inserts an Ethernet end-of-packet symbol in the data passed to the CPRI
interface module, and then stops asserting the cpri_mii_txrd signal.
While cpri_mii_txen is asserted, the cpri_mii_txer input signal indicates that the
current nibble on cpri_mii_txd is suspect. Therefore, if the MII interface transmitter
module observes that both cpri_mii_txen and cpri_mii_txer are asserted in the
same cpri_mii_txclk cycle, the MII interface module inserts an Ethernet HALT
symbol (5’b00100) in the data passed to the CPRI interface module.
page 4–56
shows how the error indication propagates to the MII interface receiver module on the
CPRI link slave.
provides an example in which the cpri_mii_txer signal is asserted, and
Figure 4–23
Figure 4–23
and to
and to
Figure
Figure
4–24.
4–24.
CPRI MegaCore Function User Guide
Figure 4–26 on
4–53