IP-CPRI Altera, IP-CPRI Datasheet - Page 107

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Software Interface
CPRI Interface Registers
Table 6–22. CPRI_INTR_PEND—Interrupt Pending Status—Offset: 0x4C (Part 2 of 2)
Table 6–23. CPRI_N_LCV—LCV Threshold—Offset: 0x50
Table 6–24. CPRI_T_LCV—LCV Test Period—Offset: 0x54
Table 6–25. CPRI_TX_PROT_VER— Tx Protocol Version —Offset: 0x58
December 2010 Altera Corporation
hw_reset_pending
RSRV
N_LCV
T_LCV
RSRV
tx_prot_version
Field
Field
Field
Field
[1]
[0]
[31:0]
[31:0]
[31:8]
[7:0]
Bits
Bits
Bits
Bits
RW
Access
RW
UR0
RW
UR0
RW
Access
Access
Access
The number of bytes in the initialization period during which
we do not yet count LCVs toward assertion of the
cpri_rx_los signal.
Indicates a hw_reset interrupt is pending (the interrupt
occurred but is not yet serviced).
In an RE slave, this bit is set when a reset request is detected
in incoming CPRI communication at Z.130.0, but neither the
reset_gen_en bit nor the reset_hw_en bit in the
CPRI_HW_RESET register is set (so that a reset acknowledge
cannot be sent to the RE master), or when the CPRI RE slave
sends a reset acknowledge on the outgoing CPRI link at
Z.130.0.
In a master, this bit is set when a reset acknowledge is
received on the incoming CPRI link at Z.130.0.
Software can count assertions of this bit to confirm the reset
bit in Z.130.0 was asserted in ten consecutive hyperframes to
complete a CPRI-compliant reset acknowledge.
Note that when a reset request is detected in incoming CPRI
communication, and the reset_hw_en bit in the
CPRI_HW_RESET register is set, the user must assert the
hw_reset_assert input signal to the CPRI RE slave, to force
it to send a reset acknowledge by setting the reset bit in
outgoing CPRI communication at Z.130.0. After the reset bit is
sent on the CPRI link, hw_reset_pending is asserted.
Reserved.
The number of LCVs that triggers the assertion of the
cpri_rx_los signal.
Reserved.
Transmit protocol version to be mapped to Z.2.0 to indicate
whether or not the current hyperframe transmission is
scrambled. The value 1 indicates it is not scrambled and the
value 2 indicates it is scrambled.
Function
Function
Function
Function
CPRI MegaCore Function User Guide
32d’614400
Default
Default
1’h1
1’h0
Default
32’h0
Default
24’h0
8’h0
6–11