IP-CPRI Altera, IP-CPRI Datasheet - Page 90

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–10
Table 5–11. CPRI MAP Transmitter Interface Signals (Part 2 of 2)
Auxiliary Interface Signals
CPRI MegaCore Function User Guide
map{23…0}_tx_status_data
Signal
Table 5–12
auxiliary interfaces. All the signals in
internal clock visible on the cpri_clkout port.
through
Output
Direction
Table 5–13
This vector contains the following status bits:
[2]
[1]
[0]
list the signals on the CPRI MegaCore function
cpri_map_tx_overflow: Tx FIFO overflow indicator for this
antenna-carrier interface. This signal is synchronous to the
cpri_clkout clock, and is asserted following a write to a full
buffer. This signal reflects the value in the appropriate bit of the
buffer_tx_overflow field of the CPRI_IQ_TX_BUF_STATUS
register
cpri_map_tx_underflow: Tx FIFO underflow indicator for
this antenna-carrier interface. This signal is synchronous to
the cpri_clkout clock, and is asserted following a read from
an empty buffer. This signal reflects the value in the
appropriate bit of the buffer_tx_underflow field of the
CPRI_IQ_TX_BUF_STATUS register
page
cpri_map_tx_en: Indicates that this antenna-carrier interface
is enabled. The value is determined in the
CPRI_IQ_TX_BUF_CONTROL register. Use this signal to disable
external logic for inactive AxC interfaces and to map interface
clock gating to save power.
6–18).
Table 5–12
(Table 6–47 on page
through
Description
Table 5–13
6–18).
December 2010 Altera Corporation
(Table 6–47 on
Auxiliary Interface Signals
are clocked by the
Chapter 5: Signals