IP-CPRI Altera, IP-CPRI Datasheet - Page 55

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
CPRI MAP Interface Module
December 2010 Altera Corporation
CPRI MAP Transmitter Interface
1
1
Because the mapN Rx buffer should not be read before it is written, the offset
specified in the CPRI_MAP_OFFSET_RX register must precede the offset specified in the
CPRI_START_OFFSET_RX register. The CPRI MegaCore function informs you of buffer
overflow and underflow (in the CPRI_IQ_RX_BUF_STATUS register described in
Table 6–46 on page
described in
Altera recommends that you implement a separate tracking protocol to ensure you do
not overflow or underflow the mapN Rx buffer.
You set the values in the CPRI_START_OFFSET_RX and CPRI_MAP_OFFSET_RX registers to
provide the correct timing to compensate for delays through the CPRI MegaCore
function. For information about delays in the Rx path through the IP core, refer to
Path Delay” on page
In synchronous buffer mode, Altera recommends that you use sample rates that are
integer multiples of 3.84 MHz, or for implementing the WiMAX protocol, that you use
sample rates that provide the exact frequency required.
The CPRI MAP transmitter interface receives data from the data channels and passes
it to the CPRI interface to transmit on the CPRI link. The CPRI MAP transmitter
implements an Avalon-ST interface protocol. Refer to
Signals” on page 5–9
CPRI MAP transmitter communication on the individual data map interfaces is
FIFO-based or synchronized, as determined by the map_tx_sync_mode field of the
CPRI_MAP_CONFIG register. In FIFO mode, each data channel, or AxC interface, has an
output ready signal, mapN_tx_ready. Each data map interface asserts its ready signal
when it is ready to receive data on this data channel for transmission to the CPRI
interface—when the buffer level is at or below the threshold indicated in the
CPRI_MAP_TX_READY_THR register. FIFO-based communication is simple but does not
allow easy control of buffer delay.
In the synchronized communication, called synchronous buffer mode, each AxC
interface has an incoming resynchronization signal, mapN_tx_resync. Application
software asserts this resynchronization signal synchronously with the mapN_tx_clk
clock. After the application software asserts the resynchronization signal, it asserts the
mapN_tx_valid signal and begins sending valid data on the mapN_tx_data[31:0] data
bus for the individual AxC interface.
In synchronous buffer mode, the application should ignore the mapN_tx_ready output
signals. However, it should assert the mapN_tx_valid input signals when sending
valid data. The CPRI MegaCore function holds the mapN_tx_ready output signals
high. The application must assert the mapN_tx_valid input signals immediately after
asserting the mapN_tx_resync signals. If the application does not assert the
mapN_tx_valid input signals high as expected, the CPRI MAP Tx interface does not
function correctly.
To ensure IP core control over the resynchronization signal timing, Altera
recommends that your application trigger the mapN_tx_resync signal with the CPRI
MegaCore function output signal cpri_tx_start. The CPRI AUX interface asserts the
cpri_tx_start signal according to the offset value specified in the
user-programmable CPRI_START_OFFSET_TX register.
Table 5–10 on page
6–18, as reported in the mapN_rx_status_data output signals
4–40.
for details of the interface communication signals.
5–7), but it does not prevent them from occurring.
“CPRI MAP Transmitter
CPRI MegaCore Function User Guide
“Rx
4–31