IP-CPRI Altera, IP-CPRI Datasheet - Page 68

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–44
Table 4–8. Fixed Latency Between Low-Level Transmitter or Receiver and the MAP or AUX Block in cpri_clkout Cycles
CPRI MegaCore Function User Guide
Rx path fixed delay (T_R1)
Tx path fixed delay (T_T4)
Direction
2. Perform the following calculation to determine the clk_ex_delay frequency that
3. Read the value of the CPRI_EX_DELAY_STATUS register at offset 0x40
4. Perform the following calculation to determine the delay through the Rx elastic
Fixed Core Delay Component
In the Rx path, the delay from the CPRI low-level receiver block to the AUX interface
or the MAP interface is fixed. In the Tx path, the delay from the AUX or MAP
interface block to the CPRI low-level transmitter block is fixed. These delays depend
on the device family and CPRI data rate.
low-level transmitter or receiver block and the MAP or AUX block.
supports your desired accuracy resolution:
clk_ex_delay period = (M/N) cpri_clkout period
Based on this calculation, the frequency of clk_ex_delay is
1/(13.123356 ns) = 76.20 MHz
The following steps assume that you run clk_ex_delay at this frequency.
page
If the rx_ex_buf_delay_valid field of the register is set to 1, the value in the
rx_ex_buf_delay field has been updated, and you can use it in the following
calculations. For this example, assume the value read from the rx_ex_buf_delay
field is 0x107D, which is decimal 4221.
buffer:
Delay through Rx elastic buffer = (rx_ex_buf_delay × cpri_clkout period) / N
This delay comprises (432.7632 ns / 13.02083 ns) = 33.236 cpri_clkout clock
cycles.
These numbers provide you the result for this particular example. For illustration,
the preceding calculation shows the result in nanoseconds. You can derive the
result in cpri_clkout clock cycles by dividing the preceding result by the
cpri_clkout clock period. Alternatively, you can calculate the number of
cpri_clkout clock cycles of delay through the Rx elastic buffer directly, as
rx_ex_buf_delay / N.
6–9).
614.4 Mbps
Arria II GX or Cyclone IV GX Device
Data Rate
4.5
5
= (128/127) (1/(76.80 MHz))
= (128/127)(13.02083 ns)
= 13.123356 ns
> 614.4 Mbps
Data Rate
5
5
= (4221 × 13.02083 ns) / 127
= 432.7632 ns
Table 4–8
shows the fixed delays between the
614.4 Mbps
Arria II GZ or Stratix IV GX Device
Data Rate
4.5
5
December 2010 Altera Corporation
Chapter 4: Functional Description
> 614.4 Mbps
(Table 6–20 on
Data Rate
Delay Measurement
3
4