IP-CPRI Altera, IP-CPRI Datasheet - Page 65

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
Figure 4–21. Rx Path Delay to AUX Output and to AxC Interfaces
December 2010 Altera Corporation
rx_datain
Transceiver
Receiver
(1a)
AUX interface or to output on the MAP interface.
between the two Rx paths.
The Rx path delay to the AUX interface is the sum of the following delays:
1. The link delay is the delay between the arrival of the first bit of a 10 ms radio
2. Delay from the CPRI low-level receiver block to the AUX interface. This delay
The Rx path delay to the MAP interface is the sum of the following delays:
1. Delay between the arrival of the first bit of a 10 ms radio frame on the CPRI Rx
frame on the CPRI Rx interface and the MegaCore function internal transmission
of the radio frame pulse from the CPRI interface Rx module. The link delay
includes the following delays:
a. Transceiver latency is a fixed delay through the deterministic latency path of
b. Delay through the clock synchronization FIFO, as well as phase misalignment
c. Byte alignment delay that can occur as data is shifted out of the Rx elastic
depends on the device family and CPRI data rate. This delay is T_R1 in
on page
interface and the MegaCore function internal transmission of the radio frame
pulse from the CPRI low-level receiver block. This delay is identical in the paths to
the AUX interface and to the MAP interface. It comprises transceiver latency and
the extended delay measurement described in the following sections, as well as a
variable byte alignment delay.
Receiver
the transceiver. Its duration depends on the device family and on the path
direction (Rx or Tx). This delay includes comma alignment. Refer to
“Transceiver Latency”
between the recovered receive clock and the core RE clock cpri_clkout. The
“Extended Rx Delay Measurement”
in the CPRI Rx elastic buffer, which includes the phase alignment delay.
buffer. This variable delay appears in the rx_byte_delay field of the
CPRI_RX_DELAY register — when the value in rx_byte_delay is non-zero, a byte
alignment delay of one cpri_clkout cycle occurs in the Rx path.
Physical Layer
4–40. Refer to
Rx Elastic
Buffer
(1b)
(1c)
AUX Interface
(2)
“Fixed Core Delay Component” on page
(2)
on the following pages.
Module
AUX
Interface Module
CPRI MAP
section shows how to calculate the delay
Figure 4–21
AxC IF 0
AxC IF n
CPRI MegaCore Function User Guide
shows the relation
Data Channels
4–44.
Figure 4–19
4–41