IP-CPRI Altera, IP-CPRI Datasheet - Page 120

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–24
Table 6–66. HDLC_RX_STATUS—HDLC Receiver Module Status—Offset: 0x300 (Part 2 of 2)
Table 6–67. HDLC_TX_STATUS—HDLC Transmitter Module Status—Offset: 0x304
Table 6–68. HDLC_CONFIG—HDLC Feature Configuration 1—Offset: 0x308 (Part 1 of 2)
CPRI MegaCore Function User Guide
rx_length
rx_abort
rx_eop
rx_ready
RSRV
tx_ready_block
rx_abort
rx_ready
RSRV
intr_tx_ready_block_en
intr_tx_abort_en
intr_tx_ready_en
intr_rx_ready_block_en
intr_rx_ready_end_en
intr_rx_abort_en
intr_rx_ready_en
intr_tx_en
intr_rx_en
intr_en
Field
Field
Field
[4:3]
[2]
[1]
[0]
[31:3] UR0
[2]
[1]
[0]
Bits
Bits
RO
RO
RO
RO
Access
RO
RO
RO
Access
[31:20] UR0
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
Bits
Reserved.
Indicates that the HDLC Tx module is ready to receive an 8-word block
of data from the HDLC channel.
Indicates the current HDLC Tx packet is aborted.
Indicates that the HDLC Tx module is ready to receive at least one
32-bit word of data from the HDLC channel.
Length of the final word in the packet. Values are:
Indicates the current HDLC Rx packet is aborted.
Indicates that the next ready data word contains the end-of-packet
byte.
Indicates that at least one 32-bit word of HDLC data is available in the
HDLC Rx buffer to be transmitted on the HDLC channel.
00: 1 valid byte
01: 2 valid bytes
10: 3 valid bytes
11: 4 valid bytes
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reserved.
Indicates an interrupt is generated when
tx_ready_block is asserted, if intr_en and
intr_tx_en are asserted.
Indicates an interrupt is generated when tx_abort is
asserted, if intr_en and intr_tx_en are asserted.
Indicates an interrupt is generated when tx_ready is
asserted, if intr_en and intr_tx_en are asserted.
Indicates an interrupt is generated when
rx_ready_block is asserted, if intr_en and
intr_rx_en are asserted.
Indicates an interrupt is generated when rx_ready_end is
asserted, if intr_en and intr_rx_en are asserted.
Indicates an interrupt is generated when rx_abort is
asserted, if intr_en and intr_rx_en are asserted.
Indicates an interrupt is generated when rx_ready is
asserted, if intr_en and intr_rx_en are asserted.
HDLC Tx interrupt enable.
HDLC Rx interrupt enable.
HDLC global interrupt enable.
Function
Function
Function
December 2010 Altera Corporation
Chapter 6: Software Interface
HDLC Registers
29'h0
1’h0
1’h0
1’h0
2’h0
1’h0
1’h0
1’h0
Default
Default
11'h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
Default