IP-CPRI Altera, IP-CPRI Datasheet - Page 112
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
IP-CPRI
Manufacturer Part Number
IP-CPRI
Description
IP CORE - Common Public Radio Interface (CPRI)
Manufacturer
Altera
Specifications of IP-CPRI
Software Application
IP CORE, Interface And Protocols, HIGH SPEED
Supported Families
Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 112 of 142
- Download datasheet (3Mb)
6–16
Table 6–36. CPRI_MAP_OFFSET_TX—MAP Tx Frame Offset—Offset: 0x11C (Part 2 of 2)
Table 6–37. CPRI_START_OFFSET_RX—Rx Start Frame Offset—Offset: 0x120
Table 6–38. CPRI_START_OFFSET_TX—Tx Start Frame Offset—Offset: 0x124
Table 6–39. CPRI_MAP_RX_READY_THR—CPRI Mapping Rx Ready Threshold—Offset: 0x128
CPRI MegaCore Function User Guide
map_tx_offset_z
map_tx_offset_x
RSRV
start_rx_hf_resync
RSRV
start_rx_offset_seq
start_rx_offset_z
start_rx_offset_x
RSRV
start_tx_hf_resync
RSRV
start_tx_offset_seq
start_tx_offset_z
start_tx_offset_x
RSRV
map_rx_ready_thr
Field
Field
Field
Field
[15:8]
[7:0]
[31:4]
[3:0]
Bits
Bits
[31:25] UR0
[24]
[23:22] UR0
[21:16] RW
[15:8]
[7:0]
[31:25] UR0
[24]
[23:22] UR0
[21:16] RW
[15:8]
[7:0]
Bits
Bits
RW
RW
RW
Access
Access
UR0
RW
RW
RW
RW
RW
RW
Access
Access
Hyperframe number for start of read of CPRI MAP transmitter AxC
container block from each enabled mapN Tx buffer. The CPRI IP
core reads the data from the mapN Tx buffer and routes it to the
CPRI frame buffer to be prepared for transmission on the CPRI link.
Basic frame number for start of read of CPRI MAP transmitter AxC
container block from each enabled mapN Tx buffer. The CPRI IP
core reads the data from the mapN Tx buffer and routes it to the
CPRI frame buffer to be prepared for transmission on the CPRI link.
Reserved.
Threshold for assertion of the mapN_rx_valid signal, for all data
channels N. The mapN_rx_valid signal is asserted only when the
MAP Rx buffer for data channel N fills beyond this threshold value.
All the MAP Rx buffers have the same depth, 16.
Reserved.
Enables synchronization every hyperframe instead of every
radio frame. When asserted, the start_rx_offset_z field is
ignored.
Reserved.
Sequence number for start of cpri_rx_start
synchronization output.
Hyperframe number for start of cpri_rx_start
synchronization output.
Basic frame number for start of cpri_rx_start
synchronization output.
Reserved.
Enables synchronization every hyperframe instead of every
radio frame. When asserted, the start_tx_offset_z field is
ignored.
Reserved.
Sequence number for start of cpri_tx_start
synchronization output.
Hyperframe number for start of cpri_tx_start
synchronization output.
Basic frame number for start of cpri_tx_start
synchronization output.
Function
Function
MAP Interface and AUX Interface Configuration Registers
Function
Function
December 2010 Altera Corporation
Chapter 6: Software Interface
Default
28’h0
4’h8
Default
8’h0
8’h0
Default
7'h0
1’h0
2'h0
6’h0
8’h0
8’h0
Default
7'h0
1’h0
2'h0
6’h0
8’h0
8’h0
Related parts for IP-CPRI
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IPTR-C2H-NIOS](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer:
Altera
Datasheet:
![IP-XAUIPCS](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE - XAUI PHY
Manufacturer:
Altera
Datasheet:
![IP-RLDRAMII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE - RLDRAM II Controller
Manufacturer:
Altera
Datasheet:
![IP-SRAM/QDRII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE - QDRII SRAM Controller
Manufacturer:
Altera
Datasheet:
![IP-LINK](/images/no-image3.png)
Part Number:
Description:
MODULE, TX/RX, W/ PSU, IP-LINK
Manufacturer:
TOPCO SNT
Datasheet:
![I2C CONTROLLER IP CORE](/images/no-image3.png)
Part Number:
Description:
I2C Controller FPGA IP Core
Manufacturer:
SYSTEM LEVEL SOLUTIONS
![IP-10GETHERNET](/photos/24/19/241934/4696150_tmb.jpg)
Part Number:
Description:
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer:
Altera
Datasheet:
![IP-NIOS](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP NIOS II MEGACORE
Manufacturer:
Altera
Datasheet: