IP-CPRI Altera, IP-CPRI Datasheet - Page 79

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
MII Interface to an External Ethernet Block
Figure 4–25. CPRI MII Interface Receiver Example
December 2010 Altera Corporation
cpri_mii_rxd[3:0]
cpri_mii_rxclk
cpri_mii_rxwr
cpri_mii_rxdv
cpri_mii_rxer
MII Interface Receiver
reset
Frame Synchronization
If cpri_mii_txen is deasserted while cpri_mii_txrd is deasserted, and is not
reasserted in the cycle following the reassertion of cpri_mii_txrd, then the CPRI MII
Interface transmitter inserts a T symbol in the packet; therefore, the external Ethernet
block must reassert cpri_mii_txen in the cycle following reassertion of
cpri_mii_txrd, during transmission of an Ethernet packet on cpri_mii_txd.
For more information about the MII interface transmitter module, refer to
Interface Transmitter Signals” on page
The MII interface receiver module receives data from the CPRI link by reading it from
the CPRI receiver module. It performs 4B/5B decoding on the 5-bit data values before
transmitting them as 4-bit data values on the MII interface.
After the CPRI MegaCore function achieves frame synchronization, the MII interface
receiver module can send data to the external Ethernet block. The MII interface
receiver module transmits the K nibble to indicate start-of-frame on the MII interface.
The J nibble of the start-of-frame is consumed by the CPRI MegaCore function, and is
not transmitted on the MII interface.
The MII interface receiver module transmits the K nibble and then the data to the
cpri_mii_rxd output data bus and asserts the cpri_mii_rxdv signal to indicate that
the data currently on cpri_mii_rxd is valid. It sends the K nibble and the data to the
cpri_mii_rxd output data bus on the rising edge of the cpri_mii_rxclk clock. During
the first cpri_mii_rxclk cycle of every new data value on cpri_mii_rxd, the MII
interface receiver module asserts the cpri_mii_rxwr signal. After the MII interface
receiver module completes sending data to the external Ethernet block, it deasserts
the cpri_mii_rxdv signal.
The cpri_mii_rxer signal indicates whether or not frame synchronization is
achieved. While asserted, it indicates to the external Ethernet block that the data
currently on cpri_mii_rxd is not valid.
Figure 4–25
Achieved
illustrates the MII interface receiver protocol.
K
D0
5–6.
D1
D2
D3
D4
CPRI MegaCore Function User Guide
D5
D6
D7
“CPRI MII
4–55