IP-CPRI Altera, IP-CPRI Datasheet - Page 53

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
CPRI MAP Interface Module
December 2010 Altera Corporation
CPRI MAP Receiver Interface
1
1
When map_mode has value 2’b01, 32-bit data samples are packed consecutively in the
payload area of the AxC container block. A data sample may span two basic frames,
as shown in timeslot 7 in
are located at the end of the AxC container block.
When map_mode has value 2’b10, each IQ data sample is considered a different AxC
container, for backward compatibility with earlier versions of the CPRI specification.
However, multiple consecutive 32-bit words in the same frame may contain data
samples from or for the same AxC interface. In other words, data to or from the same
AxC interface may appear in consecutive timeslots, even though these IQ data
samples are considered individual AxC containers. IQ data samples do not span
frames. Spare bytes not assigned to an AxC container become reserved bits. These
reserved bits are located at the end of the basic frame.
Some table entries are not available, depending on the map_mode and sample width.
For example, in
are available, and when map_mode has value 2’b10, only table entries 0–13 are
available.
The CPRI MAP receiver interface transmits to the data channels data that the CPRI
MegaCore function receives from the CPRI link. The CPRI MAP receiver implements
an Avalon-ST interface protocol. Refer to
for details of the interface communication signals.
CPRI MAP receiver communication on the individual data map interfaces is
FIFO-based or synchronized, as determined by the map_rx_sync_mode field of the
CPRI_MAP_CONFIG register. In FIFO mode, each data channel, or AxC interface, has an
output ready signal, mapN_rx_valid. Each data map interface asserts its ready signal
when it is ready to transmit data on this data channel—when the buffer level is above
the threshold indicated in the CPRI_MAP_RX_READY_THR register. FIFO-based
communication is simple but does not allow easy control of buffer delay.
In the synchronized communication, called synchronous buffer mode, each AxC
interface has a resynchronization signal, mapN_rx_resync. The application that
controls the data channel asserts its resynchronization signal synchronously with the
mapN_rx_clk clock. After the application software asserts the resynchronization
signal, it begins reading data on the mapN_rx_data[31:0] data bus for the individual
AxC interface.
In synchronous buffer mode, the application should ignore the mapN_rx_valid output
signals and hold the mapN_rx_ready input signals high. The CPRI MegaCore function
does assert the mapN_rx_valid output signals in response to the mapN_rx_ready
signals. The application must hold the mapN_rx_ready input signals high to allow the
FIFO pointers to change values. If the application does not hold the mapN_rx_ready
input signals high, the CPRI MAP Rx interface does not function correctly.
To ensure IP core control over the resynchronization signal timing, Altera
recommends that your application trigger the mapN_rx_resync signal with the CPRI
MegaCore function output signal cpri_rx_start. The CPRI AUX interface asserts the
cpri_rx_start signal according to the offset value specified in the
user-programmable CPRI_START_OFFSET_RX register.
Figure
4–13, when map_mode has value 2’b01, only table entries 0–14
Figure
4–13. Spare bits become reserved bits. Reserved bits
“CPRI MAP Receiver Signals” on page 5–7
CPRI MegaCore Function User Guide
4–29