IP-CPRI Altera, IP-CPRI Datasheet - Page 95

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Signals
Clock and Reset Interface Signals
Clock and Reset Interface Signals
Table 5–15. CPRI MegaCore Function Clock and Reset Signals
December 2010 Altera Corporation
clk_ex_delay
reset_ex_delay
config_reset
pll_clkout
cpri_clkout
hw_reset_req
hw_reset_assert
Signal
Table 5–15
described in other sections with their associated modules.
Direction
Input
Input
Input
Output
Output
Output
Input
describes the CPRI MegaCore function clock and reset signals not
Extended delay measurement clock.
Reset for extended delay measurement block.This reset is associated with the
clk_ex_delay clock.
reset_ex_delay can be asserted asynchronously, but must stay asserted at
least one clock cycle and must be de-asserted synchronously with the clock
with which it is associated. Refer to
shows how to enforce synchronous deassertion of a reset signal.
Register reset. This reset is associated with the cpri_clkout clock.
config_reset can be asserted asynchronously, but must stay asserted at
least one clock cycle and must be de-asserted synchronously with the clock
with which it is associated. Refer to
shows how to enforce synchronous deassertion of a reset signal.
Generated from transceiver clock data recovery circuit. Intended to connect to
an external PLL for jitter clean-up.
CPRI core clock. Provided for observation and debugging.
Hardware reset request detected from received reset control word. This signal
is set after the received reset control word is set in four consecutive basic
frames, if the reset_out_en bit of the CPRI_HW_RESET register is set. This
signal is cleared in reset. It can be used to inform the application layer of the
low-level reset request.
Indicates a reset request should be sent to the CPRI link partner on the CPRI
link, using bit 0 of the CPRI hyperframe control word Z.130.0. If the
reset_hw_en bit of the CPRI_HW_RESET register is set, the CPRI MegaCore
function sends the reset request on the CPRI link. The hw_reset_assert
signal is detected on the rising edge of cpri_clkout.
Description
Figure 4–8 on page 4–14
Figure 4–8 on page 4–14
CPRI MegaCore Function User Guide
for a circuit that
for a circuit that
5–15