IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 101

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Device & Board Settings
© March 2009 Altera Corporation
f
To achieve maximum performance, your design should use the fedback clock DQS
mode. You should use this mode for 267-MHz designs. However, there is no
automatic setup of the fedback PLL, or the resyncronization and postamble clock
phases in fedback clock DQS mode. Use the steps in this appendix to achieve timing
closure.
As an example, this appendix demonstrates how to close timing on an Altera Stratix II
Memory Board 2 with a Stratix II –4 speed-grade device. This appendix follows the
“MegaWizard Plug-In Manager Design Flow” on page
differences or additional steps.
For more information on the Stratix II Memory Board 2, contact your local Altera
representative.
Achieving 267 MHz on a –4 speed grade device is easier with a narrow interface,
because there is likely to be less skew across the byte groups. Achieving 267 MHz is
also easier on smaller devices than larger devices, because the clock network is faster
in small devices.
To specify the correct device and board settings, follow these steps:
1. When you create a new Quartus II project, select an EP2S60F1020C4 Stratix II
2. In the MegaWizard Plug-In Manager, expand the Interfaces > Memory
3. In the IP Toolbench—Parameterize window:
device.
Controllers directory then click DDR2 SDRAM Controller <version>.
a. On the Memory tab, in the Presets list, choose Infineon HYS72T64000GU-3.7.
b. On the Controller tab, turn on Use fedback clock and Enable DQS mode.
c. On the Board Timings tab, type the following board trace delays:
■
■
■
1
1500 ps for FPGA clock output
1500 ps for memory DQ/DQS outputs
3000 ps for the fedback clock trace, nominal delay
Use measurement or simulation to derive precise values for your board.
D. Maximizing Performance
DDR and DDR2 SDRAM Controller Compiler User Guide
2–8, but indicates the