IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 52

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–16
DLL Configurations
Table 3–4. DLL Signals
Example Design
DDR and DDR2 SDRAM Controller Compiler User Guide
clk
reset_n
delayctrlout
stratix_dll_control
dqsupdate
Note to
(1) Stratix II devices only.
Table
3–4:
(1)
Signal
For Stratix series designs, IP Toolbench creates an instance of a DLL, which is
configured to match your controller. The DLL generates the 90° phase shift on the
DQS edges that capture the read data.
On Stratix devices, the reference clock is driven off the device and fed back into the
DLL reference clock inputs (refer to
logic to allow the DLL to update only during the memory refresh period, the
controller generates a control signal, stratix_dll_control, which can enable the
DLL reference clock only while the controller is issuing refresh commands to the
memory.
On Stratix II devices, the DLL reference clock is fed directly from an enhanced PLL.
For an interface that is only on one side of the Stratix II device, the DLL automatically
generates a control signal, dqsupdate, to the DQS pins on the same side telling them
when it is safe to update their delay value. If your interface spans two sides of the
device, the controller can generate a control signal, stratix_dll_control, to only
allow the 6-bit control signal to each DQS pin to update only while the controller is
issuing refresh commands to the memory. Turning on Insert logic to allow the DLL
to update only during the memory refresh period causes the extra logic to be
inserted and should only be turned on if your interface spans two sides of the device.
Turning on this feature on a single sided interface is not required, because the DLL
controls the updates.
Table 3–4
IP Toolbench creates an example design that shows you how to instantiate and
connect up the DDR or DDR2 SDRAM controller. The example design consists of the
DDR or DDR2 SDRAM controller, some driver logic to issue read and write requests
to the controller, up to two PLLs to create the necessary clocks and a DLL (Stratix
series only). The example design is a working system that can be compiled and used
for both static timing checks and board tests.
(1)
shows the DLL signals.
The reference clock, which comes either from an external pin in Stratix devices or
from an enhanced PLL output in Stratix II devices.
The reset input.
The 6-bit output, which controls the value of the delay chain on the DQS inputs.
The control signal from the controller, which is available if you turn on Insert
logic to allow the DLL to update only during the memory refresh period. It
controls when the 6-bit control value to DQS pins updates. On Stratix devices
stratix_dll_control disables the clock output.
A DLL-generated control signal that controls when the 6-bit control value to DQS
pins updates, if the interface is only on one side of the device.
Figure 3–9 on page
Description
3–15). If you turn on Insert
Chapter 3: Functional Description
© March 2009 Altera Corporation
Device-Level Description