IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 67

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Parameters
Table 3–9. DDR & DDR2 SDRAM Interface Signals (Part 2 of 2)
Parameters
Table 3–10. Global Parameters
© March 2009 Altera Corporation
clk_to_sdram
clk_to_sdram_n
ddr_a[]
ddr_ba[]
ddr_cas_n
ddr_cke[]
ddr_cs_n[]
ddr_dm[]
ddr_odt
ddr_ras_n
ddr_we_n
Note to
(1) You can change the ddr_ signal name prefix in IP Toolbench.
Presets
Clock speed
Note to
(1) Depends on the FPGA and the memory device that you choose.
Parameter
Signal Name
Table
Table
3–9:
3–10:
Part
number or
custom
> 75
The parameters can be set only in IP Toolbench (refer to
Controller Walkthrough” on page
Value
(1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Units
MHz
—
Inverted clock for the memory device.
Memory bank address bus.
Memory column address strobe signal.
Clock for the memory device.
Memory address bus.
Memory clock enable signals.
Memory chip select signals.
Memory data mask signal, which masks individual bytes during writes.
Memory on-die termination control signal (DDR2 SDRAM only).
Memory row address strobe signal.
Memory write enable signal.
A part number for a particular memory device, module, or the name of an
Altera development board. Choosing an entry other than Custom sets many of
the parameters in the wizard to the correct value for the specified part. If any
such parameter is changed to a value that is not supported by the specified
device, the preset automatically changes to custom. You can add your own
devices or boards to this list by editing the memory_types.dat file in the
\constraints directory.
The clock frequency used by the memory controller. Because the controller
uses double data rate, the data rate is twice the clock frequency.
2–9).
Table 3–10
(Note 1)
Description
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
shows the global parameters.
“DDR & DDR2 SDRAM
3–31