IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 90

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–12
Figure A–8. Choosing the Best Postamble Phase
Intermediate Postamble Registers
DDR and DDR2 SDRAM Controller Compiler User Guide
Preset Enable Window
Preset Enable Window
Theoretical Postamble
Actual Postamble
dqs (90 shifted)
Postamble
Postamble
Figure A–8
example the best postamble phase is cycle = 0, phase = 270° , and the rising edge of
write_clk.
This example is for CAS latency = 2. For CAS latency = 2.5, add 180° to the
calculation; for CAS latency = 3, add 1 cycle.
Figure A–8
clock and the time available for the register to latch the doing_rd_delayed signal is
T1. If the time T1 is not sufficient to latch the data properly, clock the register that
outputs doing_rd_delayed signal with the positive edge of the system clock,
which is time T2 to latch the doing_rd_delayed data and is larger than T1. To latch
the data with the positive edge of the system clock, turn on Insert an intermediate
postamble register (refer to
Figure A–9. Time Between Postamble and System Clock
write_clk
o
Phase
Cycle
dq
clk
shows an example of how to choose the best postamble phase. In this
shows the postamble clock phase close to the negative edge of the system
H
Best Postamble Phase
Safe Postamble Window
L
Theoretical Round Trip Delay
System Clock
0
0
Postamble
Figure
H
Clock
180
A–9).
L
1
0
T1
180
T2
© March 2009 Altera Corporation
2
DQS Postamble