IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 6

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–2
Features
General Description
DDR and DDR2 SDRAM Controller Compiler User Guide
Table 1–2. Device Family Support (Part 2 of 2)
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The Altera DDR and DDR2 SDRAM Controller Compiler comprises the DDR SDRAM
Controller MegaCore function and the DDR2 SDRAM Controller MegaCore function.
The MegaCore functions provide simplified interfaces to industry-standard DDR
SDRAM and DDR2 SDRAM devices.
The DDR and DDR2 SDRAM Controllers handle the complex aspects of using DDR or
DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and
keeping the devices refreshed at appropriate intervals. The DDR and DDR2 SDRAM
Controllers translate read and write requests from the local interface into all the
necessary SDRAM command signals.
Other device families (2),
Notes to
(1) For new Stratix II designs, use the DDR and DDR2 SDRAM High-Performance Controller.
(2) For more information on support for Stratix III devices with existing designs, contact Altera.
(3) For new Stratix III or Cyclone III designs, use the DDR and DDR2 SDRAM High-Performance Controller.
Support for industry-standard DDR and DDR2 SDRAM devices and modules
1, 2, 4, or 8 chip-select signals
Data mask signals for partial write operations
Bank management architecture, which minimizes latency
Configurable data width
DQS read postamble control logic
Free clear-text datapath for use with custom controller
Automatic or user-controlled refresh
Support for registered DIMMs
Optional non-DQS read mode for Stratix and Stratix II side banks
IP Toolbench-generated constraint script
Quick and easy implementation with example design
System timing analysis
Support for OpenCore Plus evaluation
SOPC Builder ready
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Table
1–2:
Device Family
(3)
No support
DDR SDRAM
Support
Chapter 1: About This Compiler
March 2009 Altera Corporation
No support
DDR2 SDRAM
Features