IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 103

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Update the PLL Phases
Update the PLL Phases
© March 2009 Altera Corporation
After compilation you should return to IP Toolbench and update the PLL phases. The
verify timing script reports the margins on the various registers in the read path. To
update the PLL phases, follow these steps:
1. Edit your custom variation in IP Toolbench.
2. On the Manual Timings tab, turn on Use the results of the last comile to estimate
3. Adjust the PLL phases to meet timing.
4. Recompile the design. The verify timing script should report improved margins.
5. To balance the setup and hold margins, or to fix negative margins return to step
set_instance_assignment -name TPD_REQUIREMENT "1.6 ns" –from
*resynched_data* -to *fedback_resynched_data*'
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
setup and hold margins.
IP Toolbench uses initial estimates based on a nominal design. After you run the
verify timing script for the first time, IP Toolbench uses data from your design to
make more accurate estimates of the margins.
“Adjust the PLL Phases” on page
1
1
The calculation of setup and hold margins for the registers driven from the
fedback PLL can appear confusing—a small adjustment of the phase can
cause a large change in setup and hold margins. The timing script
automatically calculates the cycle that the data is transferred in. A small
change to the phase can change the cycle on which the data is transferred,
which results in a large change on the setup and hold margins.
If the second resynchronization path does not meet timing, or to increase
the available margin, add a maximum-data-arrival-skew constraint
between the first and second stage resynchronization registers. This
constraint constrains the routing and placement of these registers and
reduces skew across this bus. Add these constraints by executing the
following commands in the Tcl Console:
D–2.
DDR and DDR2 SDRAM Controller Compiler User Guide
D–3