IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 60

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–24
Figure 3–16. User Refresh Control
Note to
(1) DDR Command shows the command that the command signals are issuing.
DDR and DDR2 SDRAM Controller Compiler User Guide
Figure
DDR SDRAM Interface
3–16:
local_refresh_ack
local_refresh_req
DDR Command
Local Interface
ddr_cas_n
ddr_ras_n
ddr_we_n
ddr_cs_n
ddr_cke
reset_n
ddr_ba
ddr_a
2. The user logic requests a write, a read, and another write request, which are
3. The controller asserts the write data request signal to ask the user logic to present
4. The read data from the first read request is returned and marked as valid by the
5. The controller again asserts the write data request for the second write request.
6. The read data from the second read request is returned.
User Refresh Control
Figure 3–16
when the controller issues refreshes to the memory. This feature allows better control
of worst case latency and allows refreshes to be issued in bursts to take advantage of
idle periods.
1. The user logic asserts the refresh request signal to indicate to the controller that it
2. The controller asserts the refresh acknowledge signal to indicate that it has issued
3. The user logic keeps the refresh request signal asserted to indicate that it wishes to
The controller again asserts the refresh acknowledge signal to indicate that it has
issued a refresh. At this point the user logic deasserts the refresh request signal and
the controller continues with the reads and writes in its buffers.
clk
accepted.
valid write data and byte enables on the next clock edge.
read data valid signal.
should perform a refresh. The state of the read and write requests signal does not
matter as the controller gives priority to the refresh request (although it completes
any currently active reads or writes).
a refresh. This signal is still available even if the user refresh control option is not
switched on, allowing the user logic to keep track of when the controller is issuing
refreshes.
perform another refresh request.
0000
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shows the user refresh control interface. This feature allows you to control
[1]
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0400
PCH NOP ARF
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[2]
[3]
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0
0000
ARF
ARF
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[4]
Chapter 3: Functional Description
© March 2009 Altera Corporation
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Interfaces & Signals