IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 80

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–2
Table A–1. Resynchronization Options (Part 2 of 2)
Table A–2. Postamble Options (Part 1 of 2)
DDR and DDR2 SDRAM Controller Compiler User Guide
Dedicated clock phase
Fed-back clock phase
Insert intermediate
resynchronization registers
Manual postamble control
Enable DQS postamble logic
Insert intermediate
postamble registers
Postamble cycle
Parameter
Parameter
f
Table A–2
For more information on the resynchronization options, refer to
page
A–10).
0 to 359
0 to 359
On or off
On or off
On or off
On or off
0 to 6
shows the postamble options (DQS mode only).
Range
Range
When turned on, the postamble logic is used. If the
When turned on, the doing_rd_delayed signal is
This parameter is available only when you select Dedicated
for the Resynchronization clock setting. You can enter the
phase of the dedicated resynchronization clock for timing
analysis. IP Toolbench uses this value to set up the PLL
phase shift.
Allows you to enter the phase of the fed-back clock that is
used for timing analysis. IP Toolbench uses this value to set
up the PLL phase shift.
When turned on, an extra pipeline register, clocked on the
negative edge of system clock, is inserted in the read path
after the resynchronization registers. Turn on when the
resynchronization clock is too close to the system clock for
reliable transfer between them. Refer to
Resynchronization Registers” on page
Turn on to specify the details of the postamble logic clock
and to set the postamble clock phase manually. Otherwise,
the details are calculated automatically based on system
timing.
This option is only available when you turn on Enable DQS
Mode in the controller settings tab.
postamble logic is not used, there is a possibility of data loss
in the last transfer of each read burst.
Turn on to use the postamble logic. Turn off to remove the
postamble logic from the design (refer to
page 3–9
the postamble logic you may see data loss in the last transfer
of each burst read. If you turn off this option, you must
ensure the read capture occurs correctly.
generated using the positive edge of the system clock and
when turned off, doing_rd_delayed is generated using
the negative edge of the system clock. Turn on when the
negative edge of the system clock is too close to the positive
edge of the postamble clock. Refer to
Postamble Registers” on page
The number of cycles of delay to allow for round-trip delay.
to
Figure 3–7 on page
Description
Description
A–12.
© March 2009 Altera Corporation
3–12). When you turn off
“DQS Postamble” on
“Intermediate
A–10.
“Intermediate
Figure 3–4 on
Parameters