IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 76

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–40
Project Settings
Table 3–22. Example Design Options
Table 3–23. Variation Path Options
Table 3–24. Device Pin Prefixes & Names Options
DDR and DDR2 SDRAM Controller Compiler User Guide
Update the example design
file that instantiates the
controller variation
Automatically apply
datapath-specific contraints
to the Quartus II project
Automatically verify
datapath-specific timing in
the Quartus II project
Update the example design
PLLs
Enable hierarchy control
Hierarchy path to your
custom variation
Pin name of the clock
driving the memory (+)
Pin name of the clock
driving the memory (–)
Pin name of fed-back clock
input
Pin prefix all pins on the
devices with
Parameter
Parameter
Parameter
Table 3–22
Table 3–23
Table 3–24
When this option is turned on, IP Toolbench parses and updates the example design file. It
only updates sections that are between the following markers:
<<START MEGAWIZARD INSERT <tagname>
<<END MEGAWIZARD INSERT <tagname>
If you edit the example design file, ensure that your changes are outside of the markers or
remove the markers. Once you remove the markers, you must keep the file updated, because
IP Toolbench can no longer update the file.
When you turn on this option, IP Toolbench updates the example testbench and the ModelSim
simulation script.
When this option is turned on, the next time you compile, the Quartus II software
automatically runs the add constraints script. Turn off this option if you do not want the script
to run automatically
When this option is turned on, after every compilation the Quartus II software automatically
runs the verify timing script. Turn off this option if you do not want the script to run
automatically.
When this option is turned on, IP Toolbench automatically overwrites the PLLs.Turn off this
option, if you do not want the wizard to overwrite the system PLL or the optional fed-back
PLL.
The constraints script analyzes your design, to automatically extract the hierarchy to your
variation. To prevent the constraints script analyzing your design, turn on Enable hierarchy
control, and enter the correct hierarchy path to your datapath.
The hierarchy path is the path to your DDR or DDR2 SDRAM datapath, minus the top-level
name. The hierarchy entered in the wizard must match your design, because the constraints
and timing scripts rely on this path for correct operation.
The suggested clk_to_sdram pin name, which you may edit, but must end in [0].
The suggested clk_to_sdram_n pin name, which you may edit, but must end in [0].
The suggested fedback_clock_in pin name, which you may edit.
This string is used to prefix the pin names for the FPGA pins connected to the DDR or DDR2
SDRAM.
shows the example design options.
shows the variation path options.
shows the device pin prefixes and names options.
Description
Description
Description
Chapter 3: Functional Description
© March 2009 Altera Corporation
Parameters