IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 54

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–18
Constraints
DDR and DDR2 SDRAM Controller Compiler User Guide
f
1
1
1
The testbench instantiates a DDR or DDR2 SDRAM DIMM model, a reference clock
for the PLL, and model for the system board memory trace delays. When
test_complete is detected high, a test finished message is printed out, which
shows whether the test has passed.
Altera does not provide a memory simulation model. You must obtain one from your
memory vendor.
For more details on how to run the simulation script, refer to
Design” on page
IP Toolbench generates a constraints script, add_constraints_for_<variation name>.tcl,
which is a set of Quartus II assignments that are required to successfully compile the
example design.
When the constraints script runs, it creates another script,
remove_constraints_for_<variation name>.tcl, which you may use to remove the
constraints from your design.
The constraints script implements the following types of assignments:
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As the static timing analysis performed after the design compiles requires that the all
the clocks in the datapath are global, you must ensure you do not use regional clocks
for the datapath logic.
Table 3–8
Table 3–6. Methods for Logic Placement Constraints
Stratix II/Stratix II GX
Stratix/Stratix GX
Cyclone II
Cyclone
Capacitance loading for SDRAM interface pins
I/O standard to SSTL-2 class II for DDR SDRAM interface pins (SSTL-18 class II
for DDR2 SDRAM)
Current strength set to “min” for Stratix devices
DM, DQ, and DQS pin placement (except for non-DQS mode on Stratix devices)
Resynchronization and postamble registers placement
I/O register placement for Cyclone series
Synthesis “Don’t Optimize” set for the datapath logic
Address and control fast output register constraints
DQS frequency and delay settings for Cyclone devices
shows the methods that achieve the logic placement constraints.
Device Family
2–17.
LAB placement
LE placement
Capture Registers
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—
LAB placement
LogicLock region constraints
LAB placement
LE placement
Resynchronization Registers
Chapter 3: Functional Description
© March 2009 Altera Corporation
“Simulate the Example
Device-Level Description