IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 85

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Resynchronization
Figure A–3. Resynchronization Registers—Stratix Series, Non-DQS Mode
Notes to
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
© March 2009 Altera Corporation
Figure
local_rdata
PLL
Clocked by Capture Clock
Clocked by Resynchronization Clock
Clocked by System Clock
A–3:
resynch_clk
Intermediate resynchronization registers
capture_clk
Figure A–4
mode).
clk
(see Note 1)
Reclock resynchronized data
shows the resynchronization registers for Stratix II series (non-DQS
to rising edge registers
(see Note 2)
Resynchronization registers
DDR and DDR2 SDRAM Controller Compiler User Guide
Capture registers
DQ
A–7