IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 51

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Device-Level Description
Figure 3–9. Stratix PLL Configuration
Note to
(1) In most cases, clk or write_clk are used as the resynchronization and postamble clocks, therefore you need not use a separate clock output
Figure 3–10. Cyclone II PLL Configuration
Figure 3–11. Cyclone PLL Configuration
© March 2009 Altera Corporation
from the PLL.
Figure
clock_source
3–9:
clock_source
clock_source
Figure 3–10
divide ratios including a ratio of one.
Figure 3–11 on page 3–15
Stratix Device
Cyclone II Device
Cyclone Device
Enhanced PLL
PLL
PLL
shows the Cyclone II configuration for use with any PLL multiply or
C0
C1
C2
C3
C0
C1
C2
C0
C1
clk
write_clk
resynch_clk or
capture_clk
postamble_clk
(Note 1)
clk
write_clk
clk
write_clk
resynch_clk
shows the Cyclone configuration.
DDR SDRAM
Controller
DDR SDRAM
Controller
DDR SDRAM
Controller
Note 1
Stratix DLL
altddio
altddio
altddio
altddio
altddio
altddio
altddio
DDR and DDR2 SDRAM Controller Compiler User Guide
clk_to_sdram_n
clk_to_sdram_n
clk_to_sdram
clk_to_sdram
dqs_ref_clk
clk_to_sdram_n
clk_to_sdram
DDR SDRAM
DDR SDRAM
DDR SDRAM
3–15