IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 14

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–4
DDR and DDR2 SDRAM Controller Compiler User Guide
f
9. Choose the target device in the Available devices list.
10. The remaining pages in the New Project Wizard are optional. Click Finish to
Launch SOPC Builder & IP Toolbench
To launch SOPC Builder, follow these steps:
1. Choose SOPC Builder (Tools menu).
2. Enter a System Name.
3. Type a value for the clk_0 (MHz). For example, 80.0.
4. Build your system from the System Contents list. Expand the Memories and
Parameterize
To parameterize the DDR or DDR2 SDRAM Controller, follow these steps:
1. Click Step 1: Parameterize, to parameterize your custom variation.
2. In the Presets list, click a specific memory device, Altera development board, or
3. If you chose Custom, choose the appropriate Memory Interface values and enter
4. Click Show Timing Estimates, at any time to see the results of the system timing
5. You may turn on Advanced Mode at any time, to see all the settings you can
For more information on Advanced Mode settings, refer to
page
1
complete the Quartus II project.
1
Memory Controllers folder, and click either DDR SDRAM MegaCore Function
or DDR2 SDRAM MegaCore Function in the SDRAM folder. Click Add. The
DDR SDRAM controller IP Toolbench opens.
click Custom.
1
1
your Board Trace Delays.
1
analysis.
change on the DDR or DDR2 SDRAM Controller.
2–11.
If you are targeting a specific Altera development board, ensure you choose
the correct target device and memory type.
The system name must not be the same as the Quartus II project name (and
therefore the top-level design entity name).
If you chose to target an Altera board, all the settings on the Basic Settings
tab and all Advanced Mode settings are correct for that board.
You cannot alter the clock speed in IP Toolbench. To alter the clock speed of
your system, close IP Toolbench and return to step
You must accurately set the board trace delays for your system to work in
hardware.
“Parameterize” on
© March 2009 Altera Corporation
3
on
Chapter 2: Getting Started
page
SOPC Builder Design Flow
2–4.