IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 73

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Parameters
Table 3–17. DLL Reference Clock Options
Controller Timings
© March 2009 Altera Corporation
Insert logic to allow the DLL
to update only during the
memory refresh period
Parameter
Figure 3–21. Additional Pipeline Registers—A = On, B = Off, C= On
Figure 3–22. Additional Pipeline Registers—A = On, B = On, C= On
Table 3–17
The memory timing parameters on the controller timings tab adjust the controller’s
timing to meet the timing parameters specified in the datasheet for the memory
devices. The Controller Timings tab shows the following three columns of
information:
■
■
■
The Required column specifies the timing requirements from the memory device
datasheet; these requirements can be minimum or maximum times. The values in the
required column are automatically set by your chosen memory device from the
Memory Device list.
The Cycles column specifies the number of cycles that the controller uses to meet
these timing requirements.
The Actual column reports the actual time that the controller uses, based on the
values in the cycles column and the clock speed.
Required
Cycles
Actual
FSM
On or off
Range
shows the DLL reference clock options.
FSM
clk
clk
For Stratix devices, Altera recommends you turn on this option to switch
off the DLL during read operations and so reduce jitter. For Stratix II
devices, Altera recommends you turn on this option only if your memory
interface spans two sides of the device or if you intend to share a DLL
between two or more interfaces on two sides of the device. Refer to
Configurations” on page
A
addrcmd_clk
A
B
3–16.
DDR and DDR2 SDRAM Controller Compiler User Guide
B
Description
Negative Edge
Address and Command
Output
Negative Edge
Address and Command
Output
“DLL
3–37