IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 21

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation
f
Launch IP Toolbench from the MegaWizard Plug-In Manager
To launch the wizard in the Quartus II software, follow these steps:
1. Start the MegaWizard Plug-In Manager by choosing the MegaWizard Plug-In
2. Specify that you want to create a new custom megafunction variation and click
3. Expand the Interfaces > Memory Controllers directory, then click either DDR
4. Select the output file type for your design; the wizard supports VHDL and Verilog
5. The MegaWizard Plug-In Manager shows the project path that you specified in the
6. Click Next to launch IP Toolbench.
Parameterize
To parameterize your MegaCore function, follow these steps:
For more information on the parameters, refer to
1. Click Step 1: Parameterize in IP Toolbench.
2. In the Presets list, click a specific memory device, Altera development board, or
3. Enter a Clock Speed in MHz. For example 200.0. The constraints script, timing
4. Choose the memory parameters.
Manager command (Tools menu). The MegaWizard Plug-In Manager dialog box
displays.
1
Next.
SDRAM Controller v9.0 or DDR2 SDRAM Controller v9.0.
HDL.
New Project Wizard. Append a variation name for the MegaCore function output
files <project path>\<variation name>.
1
click Custom.
1
analysis, and the datapath use this clock speed. It must be set to the value that you
intend to use. The first time you use the DDR SDRAM controller IP Toolbench or if
you turn on Automatically generate the PLL, it uses this value for the IP
Toolbench-generated PLL’s input and output clocks (refer to
page
a. Choose your memory interface parameters.
b. Choose the memory properties.
c. Select either Registered DIMM or Unbuffered memory.
2–22).
Refer to Quartus II Help for more information on how to use the
MegaWizard Plug-In Manager.
The <variation name> must be a different name from the project name and
the top-level design entity name.
You can add your own memory devices to this list by editing the
memory_types.dat file in the \constraints directory.
DDR and DDR2 SDRAM Controller Compiler User Guide
“Parameters” on page
“Edit the PLL” on
3–31.
2–11