IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 45

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Device-Level Description
Figure 3–4. Stratix II DQS Group Block Diagram
Notes to
(1) This figure shows the logic for one DQ output only. A complete byte group consists of eight times the DQ logic with the DQS and DM logic.
(2) All clocks are clk, unless marked otherwise.
(3) Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the DQ pin. This inversion is automatic if
(4) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timings tab, refer to
© March 2009 Altera Corporation
you use an ALTDQ megafunction for the DQ pins.
Timing Settings” on page A–1
Figure
dqs_burst
doing_wr
doing_wr
write_clk
postamble_clk
(pipelined)
be
doing_rd
3–4:
Optional Inverter (Note 4)
resynch_clk
2
wdata_valid
doing_wr
wdata
rdata
resynched_data
16
16
Preset (asynchronous)
(Note 3)
D
D
D
EN
EN
Q
Q
Q
8
8
8
D
D
D
Q
Q
EN
EN
Q
Q
Q
D
D
dq_enable_reset
dq_capture_clk
write_clk
D
(Note 1) (2)
Optional Inverters (Note 4)
dqs_oe
dq_oe
Q
Q
D
D
D
Q
Q
D
D
Q
Q
D
D
D
D
D
DDR and DDR2 SDRAM Controller Compiler User Guide
Ao
Bo
Q
Q
Q
Q
Q
Q
Q
D
D
D
0
1
0
1
0
1
1
Q
DQS Delay
DQ IOEs
DQS IOEs
DM altddio Megafunction
DM
DQS
DQ
“Manual
3–9