CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 21

Eval Bd LP Codec W/Class D Spkr Driver

CDB42L52

Manufacturer Part Number
CDB42L52
Description
Eval Bd LP Codec W/Class D Spkr Driver
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB42L52

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L52
Primary Attributes
4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
Secondary Attributes
GUI, I2C, SPI, USB Interfaces
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42L52
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1505
DS680F1
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C
RESET
MCLK Frequency
MCLK Duty Cycle
Slave Mode
Input Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
15. See
pin Low Pulse Width
settled.
(Note 15)
“Example System Clock Frequencies” on page 76
SDOUT
LRCK
SCLK
Parameters
SDIN
Figure 3. Serial Audio Interface Timing
LOAD
t
t
s(LK-SK)
d(MSB)
t
s(SD-SK)
= 15 pF.
MCLK=12.0000 MHz
SCLK=MCLK mode
5/13/08
All Speed Modes
MSB
MSB
all other modes
//
//
//
//
//
//
//
t
h(SK-SDO)
(Note 14)
t
h
t
P
for typical MCLK frequencies.
//
t
t
t
t
Symbol
h(SK-SDO)
h(SK-SDO)
s(SDO-SK)
t
s(SDO-SK)
t
t
s(SD-SK)
s(SD-SK)
s(LK-SK)
t
t
d(MSB)
d(MSB)
1/t
1/t
1/t
1/t
F
F
t
t
h
h
s
s
P
P
P
P
MSB-1
MSB-1
t
s(SDO-SK)
(See
(See
(See
Min
ing” on page
ing” on page
ing” on page
45
45
45
40
20
30
20
20
45
45
20
30
20
20
1
-
-
-
-
-
-
“Serial Port Clock-
“Serial Port Clock-
“Serial Port Clock-
12.0000
64•F
68•F
64•F
Max
34)
34)
34)
55
55
55
52
55
55
52
-
-
-
-
-
-
-
-
-
-
CS42L52
s
s
s
Units
MHz
MHz
kHz
ms
Hz
Hz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
%
21

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