CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 38

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

38
4.12
4.12.1 I²C Control
SCL
SDA
SDA
SCL
Control Port Operation
The control port is used to access the registers, allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates using an I²C interface with the CODEC acting as a slave device.
START
START
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. The signal tim-
ings for a read and write cycle are shown in
falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition of SDA
while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42L52 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write).
The upper 7 bits of the address field are fixed at 1001010. To communicate with the CS42L52, the chip
address field, which is the first byte sent to the CS42L52, should match 1001010. The eighth bit of the
address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP),
which selects the register to be read or written. If the operation is a read, the contents of the register point-
ed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes
of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the
CS42L52 after each input byte is read and is input to the CS42L52 from the microcontroller after each
transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Figure
0
CHIP ADDRESS (WRITE)
0
1
1
CHIP ADDRESS (WRITE)
1
0
1
0
2
0
21, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
2
3
1
1
4
3
0 1 0 0
0
5
4
1
6
5
0
7
6
ACK
8
0
7
9
INCR
Figure 20. Control Port Timing, I²C Write
Figure 21. Control Port Timing, I²C Read
ACK
10 11
8
6
INCR
9
5
MAP BYTE
12 13 14 15
10 11
6
4
MAP BYTE
3
5
2
12
4
1
13 14 15
3
16
0
ACK
2
STOP
5/13/08
17 18
START
1
Figure 20
16 17 18
0
19
ACK
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
and
19
6
DATA
1
0
Figure
24 25
1
1 0 1
0
25
ACK
26 27 28
26
ACK
21. A Start condition is defined as a
27 28
7
7
DATA
DATA +1
6
0
ACK
1
0
DATA +1
7
0
7
DATA +n
6
DATA + n
7
1
0
CS42L52
0
ACK
NO
ACK
STOP
DS680F1
STOP