CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 48

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

48
6.7.3
6.7.4
6.7.5
6.8
6.8.1
ADCASEL2
7
Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
Tri-State Serial Port Interface
Determines the state of the serial port drivers.
Notes:
1. Slave/Master Mode is determined by the M/S bit in
2. When the serial port is tri-stated in master mode, the ADC and DAC serial ports are clocked internally.
Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
MIC Bias Level
Sets the output voltage level on the MICBIAS output pin.
ADC Input Select
Selects the specified analog input signal into ADCx.
INV_SWCH
0
1
BIASLVL[2:0]
000
001
010
011
100
101
110
111
ADCxSEL[2:0]
000
001
010
011
100
101
110
111
Application:
3ST_SP
0
1
ADCASEL1
6
Serial Port Status
Slave Mode
Serial Port clocks are inputs and SDOUT is output
Serial Port clocks are inputs and SDOUT is HI-Z
SPK/HP_SW pin 6 Control
Not inverted
Inverted
Output Bias Level
0.5 x VA
0.6 x VA
0.7 x VA
0.8 x VA
0.83 x VA
0.91 x VA
Reserved
Reserved
Selected Input to ADCx
AIN1x
AIN2x
AIN3x
AIN4x
PGAx - Use PGAxSEL bits
Reserved
Reserved
Reserved
“Analog Inputs” on page 26
ADCASEL0
5
PGAASEL5
(“PGA Input Mapping” on page
4
5/13/08
PGAASEL4
“Master/Slave Mode” on page
3
Master Mode
Serial Port clocks and SDOUT are outputs
Serial Port clocks and SDOUT are HI-Z
49) to select input channels
PGAASEL3
2
PGAASEL2
1
46.
CS42L52
PGAASEL1
DS680F1
0