CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 31
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CDB42L52
Manufacturer Part Number
CDB42L52
Description
Eval Bd LP Codec W/Class D Spkr Driver
Manufacturer
Cirrus Logic Inc
Specifications of CDB42L52
Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L52
Primary Attributes
4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
Secondary Attributes
GUI, I2C, SPI, USB Interfaces
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42L52
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1505
DS680F1
4.3.2
BPVOL[4:0]
Limiter
When enabled, the limiter monitors the digital input signal before the DAC and PWM modulators, detects
when levels exceed the maximum threshold settings, and lowers the master volume at a programmable
attack rate below the maximum threshold. When the input signal level falls below the maximum threshold,
the AOUT volume returns to its original level set in the Master Volume Control register at a programmable
release rate. Attack and release rates are affected by the DAC soft-ramp/zero-cross settings and sample
rate, Fs. Limiter soft-ramp and zero-cross dependency may be independently enabled/disabled.
Notes:
1. Recommended settings: Best limiting performance may be realized with the fastest attack and
2. The Limiter maintains the output signal between the MIN and MAX thresholds. As the digital input
Referenced Control
MSTxVOL[7:0].....................
PMIXxVOL[6:0] ...................
OFFTIME[2:0] .....................
ONTIME[3:0] .......................
FREQ[3:0] ...........................
BEEP[1:0]............................
BEEPMIXDIS ......................
BPVOL[4:0] .........................
Referenced Control
Limiter Controls ...................
Master Volume Control........
slowest release setting with soft ramp enabled in the control registers. The MIN bits allow the user to
set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound
as the limiter attacks and releases.
signal level changes, the level-controlled output may not always be the same but will always fall within
the thresholds.
BEEP[1:0] =
'11'
BEEP[1:0] =
'10'
BEEP[1:0] =
'01'
FREQ[3:0]
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on
until BEEP is cleared.
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
BEEP is cleared.
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
ONTIME[3:0]
Register Location
“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 63
“PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)” on page 58
“Beep Off Time” on page 60
“Beep On Time” on page 60
“Beep Frequency” on page 59
“Beep Configuration” on page 61
“Beep Mix Disable” on page 61
“Beep Volume” on page 61
Register Location
“Limiter Control 2, Release Rate (Address 28h)” on page
“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 63
Figure 13. Beep Configuration Options
5/13/08
OFFTIME[2:0]
66,
“Limiter Attack Rate (Address 29h)” on page 67
...
CS42L52
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