CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 46
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CDB42L52
Manufacturer Part Number
CDB42L52
Description
Eval Bd LP Codec W/Class D Spkr Driver
Manufacturer
Cirrus Logic Inc
Specifications of CDB42L52
Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L52
Primary Attributes
4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
Secondary Attributes
GUI, I2C, SPI, USB Interfaces
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42L52
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1505
46
6.5.6
6.6
6.6.1
6.6.2
6.6.3
6.6.4
M/S
7
Interface Control 1 (Address 06h)
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
Note:
Master/Slave Mode
Configures the serial port I/O clocking.
SCLK Polarity
Configures the polarity of the SCLK signal.
ADC Interface Format
Configures the digital interface format for data on SDOUT.
DSP Mode
Configures a data-packed interface format for both the ADC and DAC.
Notes:
1. Select the audio word length using the AWL[1:0] bits
2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode
MCLKDIV2
0
1
Application:
M/S
0
1
INV_SCLK
0
1
ADCDIF
0
1
Application:
DSP
0
1
Application:
is enabled.
INV_SCLK
In slave mode, this bit is ignored when the AUTO bit
6
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 34
Serial Port Clocks
Slave (input ONLY)
Master (output ONLY)
SCLK Polarity
Not Inverted
Inverted
ADC Interface Format
Left Justified
I²S
“Digital Interface Formats” on page 36
DSP Mode
Disabled
Enabled
“DSP Mode” on page 36
ADCDIF
5
DSP
4
5/13/08
DACDIF1
3
(“Audio Word Length” on page
(“Auto-Detect” on page
DACDIF0
2
AWL1
1
44) is disabled.
47).
CS42L52
AWL0
DS680F1
0