CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 69

Eval Bd LP Codec W/Class D Spkr Driver

CDB42L52

Manufacturer Part Number
CDB42L52
Description
Eval Bd LP Codec W/Class D Spkr Driver
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB42L52

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L52
Primary Attributes
4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
Secondary Attributes
GUI, I2C, SPI, USB Interfaces
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42L52
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1505
DS680F1
6.34.2 ALC Minimum Threshold
6.35
6.35.1 Noise Gate All Channels
6.35.2 Noise Gate Enable
NGALL
7
Noise Gate Control (Address 2Dh)
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at the re-
lease rate (ALCRRATE -
CMIN thresholds.
Notes:
1. This setting is usually set slightly below the ALCMAX threshold.
Sets which channels are attenuated when clipping on any single channel occurs.
Configures the noise gate.
ALCMIN[2:0]
000
001
010
011
100
101
110
111
Application:
NGALL
0
1
Application:
NG
0
1
Application:
NG
6
Threshold Setting
0 dB
-3 dB
-6 dB
-9 dB
-12 dB
-18 dB
-24 dB
-30 dB
“Automatic Level Control (ALC)” on page 27
Noise Gate triggered by:
Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for
both channels.
Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to
take effect.
“Noise Gate” on page 28
Noise Gate Status
Disabled
Enabled
“Noise Gate” on page 28
NG_BOOST
5
“ALC Release Rate” on page
THRESH2
4
5/13/08
THRESH1
3
68) until levels lie between the ALCMAX and AL-
THRESH0
2
NGDELAY1
1
CS42L52
NGDELAY0
0
69

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