CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 26

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

26
4.2
Referenced Control
Analog Front End
PDN_PGAx .........................
PGAxVOL[5:0].....................
ADCB=A ..............................
ANLGSFTx ..........................
ANLGZCx ............................
ADCxSEL[2:0] .....................
PGAxSEL5,4,3,2,1 ..............
BIASLVL[2:0] .......................
PDN_BIAS...........................
PDN_ADCx .........................
PDN_CHRG ........................
INV_ADCx ...........................
HPFRZx...............................
HPFx ...................................
HPFx_CF[1:0]......................
ADCxOVFL..........................
Digital Volume
ADCxMUTE.........................
ADCxVOL............................
ALCx....................................
ALCxSRDIS.........................
ALCxZCDIS.........................
ALCARATE[5:0]...................
ALCRRATE[5:0] ..................
MAX[2:0]..............................
MIN[2:0]...............................
NGALL.................................
NG .......................................
THRESH[3:0].......................
NGDELAY[1:0] ....................
Miscellaneous
DIGSUM[1:0] .......................
DIGMUX ..............................
DIGM IX
Analog Inputs
DIGSUM [1:0]
Swap/
Mix
Register Location
“Power Down PGAx” on page 42
“PGAx Volume” on page 56
“Analog Front-End Volume Setting B=A” on page 50
“Ch. x Analog Soft Ramp” on page 49
“Ch. x Analog Zero Cross” on page 49
“ADC Input Select” on page 48
“PGA Input Mapping” on page 49
“MIC Bias Level” on page 48
“Power Down MIC Bias” on page 43
“Power Down ADCx” on page 43
“Power Down ADC Charge Pump” on page 42
“Invert ADC Signal Polarity” on page 51
“ADCx High-Pass Filter Freeze” on page 49
“ADCx High-Pass Filter” on page 49
“HPF x Corner Frequency” on page 50
“ADCx Overflow (Read Only)” on page 71
“ADC Mute” on page 51
“ADCx Volume” on page 57
“ALCx Enable” on page 67
“ALCx Soft Ramp Disable” on page 55
“ALCx Zero Cross Disable” on page 56
“ALC Attack Rate” on page 67
“ALC Release Rate” on page 68
“ALC Maximum Threshold” on page 68
“ALC Minimum Threshold” on page 69
“Noise Gate All Channels” on page 69
“Noise Gate Enable” on page 69
“Noise Gate Threshold and Boost” on page 70
“Noise Gate Delay Timing” on page 70
“Digital Sum” on page 50
“Digital MUX” on page 50
ALCARATE[5:0]
ALCRRATE[5:0]
MAX[2:0]
M IN[2:0]
ALCA
ALCASRDIS
ALCAZCDIS
ALCB
ALCBSRDIS
ALCBZCDIS
ADCAMUTE
DIGSFT
DIGZC
ADCAVOL[7:0]
+24/-96dB
1dB steps
ADCBM UTE
DIGSFT
DIGZC
ADCBVOL[7:0]
+24/-96dB
1dB steps
Figure 5. Analog Input Signal Flow
ALC
TO DSP Engine
FROM DSP ENGINE
Gain Adjust
Gain Adjust
HPFRZA
HPFA
HPFA_CF[1:0]
Noise Gate
5/13/08
`
HPFRZB
HPB
HPFB_CF[1:0]
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
PDN_ADCA
INV_ADCA
PDN_CHRG
PDN_ADCB
INV_ADCB
PDN_CHRG
ADCBSEL[2:0]
ADC
ADCASEL[2:0]
ADC
PDN_PGAA
PGAAVOL[5:0]
ADCB=A
ANLGSFTA
ANLGZCA
PDN_PGAB
PGABVOL[5:0]
ADCB=A
ANLGSFTB
ANLGZCB
ANALOG PASS THRU TO
HEADPHONE AM PLIFIER M UX
“M IC Inputs”
“M IC Inputs”
BIASLVL[2:0]
PDN_BIAS
Refer to
Refer to
= PGAASEL[5:1]
= PGABSEL[5:1]
Σ
Σ
CS42L52
AIN4B/ MIC2+/
MIC2B
AIN3B/MIC2-/
MIC1B
AIN2B
AIN1B
DS680F1
AIN1A
AIN2A
AIN3A/MIC1-/
MIC1A
AIN4A/ MIC1+/
MIC2A
MICBIAS