LE58QL061BVC Zarlink, LE58QL061BVC Datasheet

LE58QL061BVC

Manufacturer Part Number

LE58QL061BVC

Description

QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE

Manufacturer

Zarlink

Datasheet

1.LE58QL061.pdf (92 pages)

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APPLICATIONS

FEATURES

ORDERING INFORMATION

NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and

technology of Legerity Holdings.

Le58QL061FJC

Le58QL061BVC

Le58QL063HVC

Codec function on telephone switch line cards

Low-power, 3.3 V CMOS technology with 5 V tolerant

digital inputs

Pin programmable PCM/MPI or GCI interface

Software and coefficient compatible to the Le79Q061/

063 QSLAC device

Standard PCM/microprocessor interface

(PCM/MPI mode)

— Single or Dual PCM ports available

— Time slot assigner (up to 128 channels per port)

— Clock slot and transmit clock edge options

— Optional supervision on the PCM highway

— 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176,

— µP access to PCM data

— Real Time Data with interrupt (open drain or TTL)

— Broadcast mode

General Circuit Interface (GCI mode)

— Control and PCM data on a single port

— 2.048 Mbits/s data rate

— 2.048 MHz or 4.096 MHz clock option

Performs the functions of four codec/filters

Software programmable:

— SLIC device input impedance and Transhybrid balance

— Transmit and receive gains and Equalization

— Programmable Digital I/O pins with debouncing

A-law, µ-law, or linear coding

Built-in test modes with loopback, tone generation,

and µP access to PCM data

Mixed state (analog and digital) impedance scaling

Performance guaranteed over a 12 dB gain range

Supports multiplexed SLIC device outputs

256 kHz or 293 kHz chopper clock for Legerity SLIC

devices with switching regulator

Maximum channel bandwidth for V.90 modems

The green package meets RoHS Directive 2002/95/EC of the

European Council to minimize the environmental impact of

electrical equipment.

For delivery using a tape and reel packing system, add a "T" suffix

to the OPN (Ordering Part Number) when placing an order.

Device

or 8.192 MHz master clock derived from MCLK or PCLK

Voice Solution

44-pin PLCC

44-pin TQFP

64-pin LQFP

Package (Green)

Quad Low Voltage Subscriber Line Audio-Processing Circuit

Tube

Tray

Packing

RELATED LITERATURE

DESCRIPTION

The Le58QL061/063 Quad Low Voltage Subscriber Line

Audio-Processing Circuit (QLSLAC™) devices integrate the

key functions of analog line cards into high-performance, very-

programmable, four-channel codec-filter devices. The

QLSLAC devices are based on the proven design of Legerity’s

reliable SLAC™ device families. The advanced architecture of

the QLSLAC devices implements four independent channels

and employs digital filters to allow software control of

transmission, thus providing a cost-effective solution for the

audio-processing function of programmable line cards. The

QLSLAC devices are software and coefficient compatible to the

QSLAC devices.

A dv a n c e d s u b m i c r o n C M O S t e c h n o lo g y m ak e s t h e

Le58QL061/063 QLSLAC devices economical, with both the

functionality and the low power consumption needed in line

card designs to maximize line card density at minimum cost.

When used with four Legerity SLIC devices, a QLSLAC device

provides a complete software-configurable solution to the

BORSCHT functions.

The Le58QL061/063 device supports the feature set of the

Le58QL02/021/031 device and provides a General Circuit

Interface as a programmable mode.

BLOCK DIAGRAM

080753 Le58QL02/021/031 QLSLAC

080761 QSLAC™ to QLSLAC™ Design Conversion

Guide

080758 QSLAC™ to QLSLAC™ Guide to New Designs

CHCLK

Analog

VOUT

SLIC

VREF

CD1

CD2

CD1

CD2

CD1

CD2

CD1

CD2

VIN

Le58QL061/063

Signal Processing

Channel 1 (CH 1)

Channel 2 (CH 2)

Channel 3 (CH 3)

Channel 4 (CH 4)

Interface

SLIC

(SLI)

Document ID# 080754

Rev:

Distribution:

Reference

Circuits

Clock

Microprocessor Interface

Public Document

GCI Control Logic &

PMC & GCI Interface

Time Slot Assigner

(MPI)

(TSA)

VE580 Series

™

Date:

Version: 2

Data Sheet

GCI/PCM

DXA/DU

Interface

DRA/DD

TSCA

DXB

DRB

TSCB

FS/FSC

DCLK/S0

CS/PG

DIO/S1

INT

RST

PCLK/DCL

MCLK/E1

Sep 18, 2007

™

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