LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 82

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

PROGRAMMABLE FILTERS
General Description of CSD Coefficients
The filter functions are performed by a series of multiplications and accumulations. A multiplication occurs by repeatedly shifting
the multiplicand and summing the result with the previous value at that summation node. The method used in the QLSLAC device
is known as Canonic Signed Digit (CSD) multiplication and splits each coefficient into a series of CSD coefficients.
Each programmable FIR filter section has the following general transfer function:
where the number of taps in the filter = n + 1.
The transfer function for the IIR part of Z and B filters:
The transfer function of the IIR part of the R filter is:
The values of the user-defined coefficients (h
general equation:
where:
The value of h
1)
2)
The limit on the negative powers of 2 is determined by the length of the registers in the ALU.
The coefficient h
the right part decimal fractions, and a decimal point separates them. The first binary 1 is shifted M
point; the second binary 1 is shifted M
decimal point, and so on.
When M
front of the decimal point, giving a total value of binary 10 in front of the decimal point (i.e., a decimal value of 2.0). The value of
N, therefore, determines the range of values the coefficient h
and if N = 4 the values are between ±4).
Detailed Description of QLSLAC Device Coefficients
The CSD coding scheme in the QLSLAC device uses a value called mi, where m1 represents the distance shifted right of the
decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary 1, and m3 represents the
number of shifts to the right of the second binary 1. Note that the range of values determined by N is unchanged. Equation 4 is
now modified (in the case of N = 4) to:
where:
M
M
HI z ( )
HI z ( )
HF z ( )
h
h
h
h
1
2
i
i
i
i
= m1
= m1 + m2
=
=
=
=
B
B
C1 2
C1 2
=
=
=
1
1
Mi = the number of shifts = Mi ≤ Mi + 1
B
N = number of CSD coefficients.
±1.0 multiplied by 2
±1.0 multiplied by 1, or 1/2, or 1/4 … 1/128 …
1
---------------------------------- -
1 h
---------------------------------- -
1 h
2
2
i
h
is 0, the value is a binary 1 in front of the decimal point, that is, no shift. If M
•
•
–
–
–
–
= sign = ±1
0
m1
M1
1 z
+
–
–
(
(
–
m1
i
m1
+
n
n
h
+
1
in Equation 4 represents a decimal number, broken down into a sum of successive values of:
+
+
1
i
B
B
{
z
–
in Equation 4 is a value made up of N binary 1s in a binary register where the left part represents whole numbers,
+
1
1
2
1
2
1
–
)
)
2
C1 C
z
z
2
1
+
–
–
–
–
+
m2
1
1
M2
C2 2
h
• 2 2
2
+
+
z
•
–
B
…
2
–0
3
•
–
+
2
+
m2
, or 2
–
…
–
B
m3
(
B
B
[
m1
N
1
1
2
+
2
+
–1
+
= C1
= C1 • C2
h
–
+
B
MN
n
C3 2
, or 2
m2
2
z
4
–
2
bits to the right of the decimal point; the third binary 1 is shifted M
)
n
•
–
+
m4
–2
C1 C
–
m3
… 2
i
) are assigned via the MPI. Each of the coefficients (h
• 2 C
(
1
–7
+
…
• 3 2
C4 2
Zarlink Semiconductor Inc.
Equation 1
Equation 2
Equation 3
Equation 4
Equation 5
•
•
–
m4
–
(
i
m1
can take (e.g., if N = 3 the maximum and minimum values are ±3,
)
82
]
}
+
m2
+
m3
)
+
C1 C2
•
•
2
C3 C4 2
is also 0, the result is another binary 1 in
•
•
1
bits to the right of the decimal
–
(
i
m1
) is defined in the following
+
m2
3
bits to the right of the
+
m3
+
m4
Equation 6
Equation 7
)