LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 34

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

Debounce Filters Operation
Each channel is equipped with two debounce filter circuits to buffer the logic status of the CD1 and CD2/CD1B bits of the SLIC
device Input Data Register (MPI Command 53h and GCI Command SOP 10) before providing filtered bit’s outputs to the Real-
Time Data Register (MPI Command 4D/4Fh or GCI Command SOP 13). One filter is used only for the CD1 bit. The other filter
either acts upon the CD1B bit if E1 multiplexing is enabled or on the CD2 bit if the multiplexing is not enabled.
The CD1 bit normally contains SLIC device loop-detect status. The CD1 debouncing time is programmable with the Debounce
Time Register (MPI Command C8/C9h or GCI Command SOP 11), and even though each channel has its own filter, the
programmed value is common to all four channels. This debounce filter is initially clocked at the frame sync rate of 125 µs, and
any occurrence of changing data at this sample rate resets a programmable counter. This programmable counter is clocked at a
1 ms rate, and the programmed count value of 0 to 15 ms, as defined by the Debounce Time Register, must be reached before
updating the CDA bit of the Real Time Data register with the CD1 state. Refer to Figure 22a for this filter’s operation.
The ground-key filter (Figure 22b) provides a buffering of the signal, normally ground-key detect, which appears in the CD1B bit
of the Real-Time Data Register and the SC upstream channel in GCI mode. Each channel has its own filter, and each filter’s time
can be individually programmed. The input to the filter comes from either the CD2 bit of the SLIC device I/O Data Register (MPI
Command 53h), when E1 multiplexing is not enabled, or from the CD1B bit of that register when E1 multiplexing is enabled. The
feature debounces ground-key signals before passing them to the Real Time Data Register, although signals other than ground-
key status can be routed to the CD2 pin and then through the registers.
The ground-key debounce filter operates as a duty-cycle detector and consists of an up/down counter which can range in value
between 0 and 6. This six-state counter is clocked by the GK timer at the sampling period of 1–15 ms, as programmed by the
value of the four GK bits (GK3, GK2, GK1, GK0) of the Ground-Key Filter Data register (MPI Command E8/E9h, GCI Command
SOP 12). This sampling period clocks the counter, which buffers the CD2/CD1B bit’s status before it is valid for presenting to the
CDB bit of the Real Time Data Register. When the sampled value of the ground-key (or CD2) input is high, the counter is
incremented by each clock pulse. When the sampled value is low, the counter is decremented. Once the counter increments to
its maximum value of 6, it sets a latch whose output is routed to the corresponding CDB bit. If the counter decrements to its
minimum value of 0, this latch is cleared and the output bit is set to zero. All other times, the latch (and the CDB status) remains
in its previous state without change. It therefore takes at least six consecutive GK clocks with the debounce input remaining at
the same state to effect an output change. If the GK bit value is set to zero, the buffering is bypassed and the input status is
passed directly to CDB.
(CD1 Pin Input)
GK Enable
DET Output
from SLIC
CD1 Pin
Input Data
CD1
Register
Operation
LD Enable
CD1B
Register
Operation
E1
Contains
Valid LD
Tracks
DET State
Status
Hold Last State
Figure 21. E1 Multiplex Internal Timing
CD1 Pin
15.625 µs
Ignored
State
Zarlink Semiconductor Inc.
31.25 µs
Hold Last State
DET State
15.625 µs
34
Contains
Valid GK
Tracks
Status
4.923 kHz (64 kHz/13) pulse rate
Pulse Period 203.125 µs
15.625 µs
Hold Last State
CD1 Pin
Ignored
State
Contains
Valid LD
Tracks
DET State
Status