LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 38

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

Le58QL061/063
Data Sheet
Gain Adjustment
The QLSLAC device’s transmit path has three programmable gain blocks. Gain block GIN is an attenuator with a gain of GIN
(see
Electrical Characteristics, on page 13
for the value). Gain block AX is an analog gain of 0 dB or 6.02 dB (unity gain or gain
of 2.0), located immediately before the A/D converter. GX is a digital gain block that is programmable from 0 dB to +12 dB, with
a worst-case step size of 0.1 dB for gain settings below +10 dB, and a worst-case step size of 0.3 dB for gain settings above +10
dB. The filters provide a net gain in the range of 0 dB to 18 dB.
The QLSLAC device receive path has two programmable loss blocks. GR is a digital loss block that is programmable from 0 dB
to 12 dB, with a worst-case step size of 0.1 dB. Loss block AR is an analog loss of 0 dB or 6.02 dB (unity gain or gain of 0.5),
located immediately after the D/A converter. This provides a net loss in the range of 0 dB to 18 dB.
An additional 6 dB attenuation is provided as part of GR, which can be inserted by setting the LRG bit of MPI Command 70/71h,
GCI Command SOP 5. This allows writing of a single bit to introduce 6 dB of attenuation into the receive path without having to
reprogram GR. This 6 dB loss is implemented as part of GR and the total receive path attenuation must remain in the specified 0 to –
12 dB range. If the LRG bit is set, the programmed value of GR must not introduce more than an additional 6 dB attenuation.
Transmit Signal Processing
In the transmit path (A/D), the analog input signal (VIN) is A/D converted, filtered, companded (for A-law or µ-law), and made
available to the PCM highway or General Circuit Interface (GCI). Linear mode is only available in the PCM/MPI mode. If linear
form is selected, the 16-bit data will be transmitted in two consecutive time slots starting at the programmed time slot. The signal
processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The B, X, and GX blocks are user-
programmable digital filter sections with coefficients stored in the coefficient RAM, while AX is an analog amplifier that can be
programmed for 0 dB or 6.02 dB gain. The B, X, and GX filters can also be operated from an alternate set of default coefficients
stored in ROM (MPI Command 60/61h, GCI Command SOP 7).
The decimator reduces the high input sampling rate to 16 kHz for input to the B, GX, and X filters. The X filter is a six-tap FIR
section which is part of the frequency response correction network. The B filter operates on samples from the receive signal path
in order to provide transhybrid balancing in the loop. The high-pass filter rejects low frequencies such as 50 Hz or 60 Hz, and
may be disabled.
Transmit PCM Interface (PCM/MPI Mode)
In PCM/MPI mode, the transmit PCM interface transmits a 16-bit linear code (when programmed) or an 8-bit compressed code
from the digital A-law/µ-law compressor. Transmit logic controls the transmission of data onto the PCM highway through output
port selection and time/clock slot control circuitry. The linear data requires two consecutive time slots, while a single time slot is
required for A-law/µ-law data.
In the PCM Signaling state (SMODE = 1), the transmit time slot following the A-law or µ-law data is used for signaling information.
The two time slots form a single 16-bit data block.
The frame sync (FS) pulse identifies time slot 0 of the transmit frame and all channels (time slots) are referenced to it. The logic
contains user-programmable Transmit Time Slot and Transmit Clock Slot registers.
The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature
allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system. The data is transmitted in bytes,
with the most significant bit first.
The Clock Slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 PCLK periods to
eliminate any clock skew in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero
remainder, R, and when the transmit clock slot is greater than R. In that case, the R-bit fractional time slot after the last full time
slot in the frame will contain random information and will have the TSC output turned on. For example, if the PCLK frequency is
1.544 MHz (R = 1) and the transmit clock slot is greater than 1, the 1-bit fractional time slot after the last full time slot in the frame
will contain random information, and the TSC output will remain active during the fractional time slot. In such cases, problems
can be avoided by not using the last time slot.
The PCM data may be user programmed for output onto either the DXA or DXB port or both ports simultaneously.
Correspondingly, either TSCA or TSCB or both are Low during transmission.
The DXA/DXB and TSCA/TSCB outputs can be programmed to change either on the negative or positive edge of PCLK.
Transmit data can also be read through the microprocessor interface using Command CDh.
Data Upstream Interface (GCI Mode)
In the GCI mode, the Data Upstream (DU) interface transmits a total of 4 bytes per GCI channel. Two bytes are from the A-law
or µ-law compressor, one for voice channel 1, one for voice channel 2, a single Monitor channel byte, and a single SC channel
byte. Transmit logic controls the transmission of data onto the GCI bus as determined by the frame synchronization signal (FSC)
and the S0 and S1 channel select bits. No signaling or Linear mode options are available when GCI mode is selected.
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Zarlink Semiconductor Inc.