LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 65

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

n
Figure 29 and Figure 30 are state diagrams that define the operation of the monitor transmitter and receiver sections in the
QLSLAC device.
Figure 28 shows that transmission is initiated by the transition of the transmitter MX bit from the inactive to the
active state. The transition coincides with the beginning of the first byte sent on the monitor channel. The receiver
acknowledges the first byte by setting MR bit to active and keeping it active for at least one more frame.
The same data must be received in two consecutive frames in order to be accepted by the receiver.
The same byte is sent continuously in each of the succeeding frames until either a new byte is transmitted, the end
of message, or an abort.
Any false MX or MR bit received by the receiver or transmitter leads to a request for abort or an abort, respectively.
For maximum data transfer speed, the transmitter anticipates the falling edge of the receiver's acknowledgment, as
shown in Figure 28.
MR ... MR - bit received
MX ... MX - bit calculated and expected on the DU line
RQT ... Request for transmission from internal source
Initial
state
Figure 29. Monitor Transmitter Mode Diagram
MR
ACK, MX=1
ACK, MX=0
nth byte
1st byte
wait for
MX=1
MX=0
Idle
MR RQT
MR RQT
Zarlink Semiconductor Inc.
MR RQT
⋅
⋅
⋅
MR RQT
65
⋅
MR
MR RQT
⋅