LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 50

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits
RSVD
Channel Status (Read status only, write as 0)
Clock Fail (Read status only, write as 0) (Global status bit)
I/O Direction (Read/Write)
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually.
* Power Up and Hardware Reset (RST) Value = 00h
60/61h Write/Read Operating Functions
Linear Code
A-law or µ-law
GR Filter
GX Filter
X Filter
Command
I/O Data
Command
Input Data
MPI Command
R/W = 0: Write
R/W = 1: Read
MPI Command
R/W = 0: Write
R/W = 1: Read
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
CSTAT = 0
CSTAT = 1
CFAIL* = 0
CFAIL = 1
* The CFAIL bit is independent of the Channel Enable Register.
IOD5 = 0*
IOD5 = 1
IOD4 = 0*
IOD4 = 1
IOD3 = 0*
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
IOD1 = 1
C/L = 0*
C/L = 1
A/µ = 0*
A/µ = 1
EGR = 0*
EGR = 1
EGX = 0*
EGX = 1
EX = 0*
Channel is inactive (Standby state).
Channel is active.
The internal clock is synchronized to frame synch.
The internal clock is not synchronized to frame synch.
C5 is an input
C5 is an output
C4 is an input
C4 is an output
C3 is an input
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
Compressed coding
Linear coding
A-law coding
µ-law coding
Default GR filter enabled
Programmed GR filter enabled
Default GX filter enabled
Programmed GX filter enabled
Default X filter enabled
RSVD
D
0
C/L
D
7
0
7
Zarlink Semiconductor Inc.
CSTAT
D
A/µ
1
D
1
6
6
50
CFAIL
EGR
D
D
0
1
5
5
IOD5
EGX
D
D
1
0
4
4
IOD4
EX
D
D
0
0
3
3
IOD3
ER
D
D
1
0
2
2
IOD2
EZ
D
D
0
0
1
1
IOD1
R/W
R/W
D
EB
D
0
0